參數(shù)資料
型號(hào): LP62S1024BM-55LLT
廠商: AMIC Technology Corporation
英文描述: 128K X 8 BIT LOW VOLTAGE CMOS SRAM
中文描述: 128K的× 8位低電壓CMOS的SRAM
文件頁(yè)數(shù): 12/18頁(yè)
文件大小: 197K
代理商: LP62S1024BM-55LLT
LP62S1024B-T Series
PRELIMINARY
(October, 2002, Version 0.1)
11
AMIC Technology, Corp.
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
30pF
* Including scope and jig.
* Including scope and jig.
C
L
TTL
5pF
C
L
TTL
Data Retention Characteristics
(T
A
= -25
°
C to 85
°
C)
Figure 1. Output Load
Figure 2. Output Load for t
CLZ1
,
CLZ2
, t
OHZ
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
WHZ
, and t
OW
Symbol
Parameter
Min.
Max.
Unit
Conditions
V
DR1
2.0
3.6
V
CE1
VCC - 0.2V
V
DR2
VCC for Data Retention
2.0
3.6
V
CE2
0.2V,
I
CCDR1
Data Retention Current
-
3*
μ
A
VCC = 2V,
CE1
VCC - 0.2V,
V
IN
0V
I
CCDR2
-
3*
μ
A
VCC = 2V,
CE2
0.2V,
V
IN
0V
t
CDR
Chip Disable to Data Retention Time
0
-
ns
See Retention Waveform
t
R
Operation Recovery Time
5
-
ms
*
LP62S1024B-55LLT/70LLT
I
CCDR
: max. 3
μ
A at T
A
= 0
°
C to + 40
°
C
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