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參數(shù)資料
| 型號： | LP62S1664C |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 64K X 16 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 64K的× 16位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 148K |
| 代理商： | LP62S1664C |
LP62S1664C Series
PRELIMINARY
(February, 2002, Version 0.0)
10
AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
t
WC
t
AW
Address
DATA IN
DATA OUT
WE
HB, LB
CE
t
WR
3
t
CW
t
BW
2
t
AS
1
t
WP
t
DW
t
DH
t
OW
t
WHZ
4
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
, t
BW
) of a low CE, WE and (HB and, or LB ).
3. t
WR
is measured from the earliest of CE or WE or (HB and, or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
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