參數資料
型號: LPC1342FHN33,518
廠商: NXP Semiconductors
文件頁數: 54/74頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 16KB FLASH 32HVQFN
標準包裝: 4,000
系列: LPC13xx
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 72MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART,USB
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數: 28
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數據轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 帶卷 (TR)
LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
58 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
10.8 USB interface (LPC1342/43 only)
[1]
Characterized but not implemented as production test. Guaranteed by design.
Table 20.
Dynamic characteristics: USB pins (full-speed)
CL = 50 pF; Rpu = 1.5 k
Ω on D+ to VDD, unless otherwise specified. 3.0 V VDD 3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
10 % to 90 %
8.5
-
13.8
ns
tf
fall time
10 % to 90 %
7.7
-
13.7
ns
tFRFM
differential rise and fall time
matching
tr /tf
--
109
%
VCRS
output signal crossover voltage
1.3
-
2.0
V
tFEOPT
source SE0 interval of EOP
160
-
175
ns
tFDEOP
source jitter for differential transition
to SE0 transition
2-
+5
ns
tJR1
receiver jitter to next transition
18.5
-
+18.5
ns
tJR2
receiver jitter for paired transitions
10 % to 90 %
9-
+9
ns
tEOPR1
EOP width at receiver
must reject as
EOP; see
-
ns
tEOPR2
EOP width at receiver
must accept as
EOP; see
-
ns
Fig 31. Differential data-to-EOP transition skew and EOP width
002aab561
TPERIOD
differential
data lines
crossover point
source EOP width: tFEOPT
receiver EOP width: tEOPR1, tEOPR2
crossover point
extended
differential data to
SE0/EOP skew
n
× TPERIOD + tFDEOP
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