參數(shù)資料
型號(hào)： LPC1346FHN33,551
廠商： NXP Semiconductors
文件頁數(shù)： 20/77頁
文件大?。?/td> 0K
描述： MCU 32BIT ARM 48KB FLASH 32HVQFN
標(biāo)準(zhǔn)包裝： 260
系列： LPC13xx
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 72MHz
連通性： I²C，Microwire，SPI，SSI，SSP，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 26
程序存儲(chǔ)器容量： 48KB（48K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 10K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VQFN 裸露焊盤
包裝： 托盤
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
27 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
7.8.1 Features
GPIO pins can be configured as input or output by software.
All GPIO pins default to inputs with interrupt disabled at reset.
Pin registers allow pins to be sensed and set individually.
Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
Port interrupts can be triggered by any pin or pins in each port.
7.9 USB interface
Remark: The USB interface is available on parts LPC1345/46/47 only.
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC1345/46/47 USB interface consists of a full-speed device controller with on-chip
PHY (PHYsical layer) for device functions.
Remark: Configure the LPC1345/46/47 in default power mode with the power profiles
before using the USB (see Section 7.18.5.1). Do not use the USB with the part in
performance, efficiency, or low-power mode.
7.9.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
7.9.1.1
Features
Dedicated USB PLL available.
Fully compliant with USB 2.0 specification (full speed).
Supports 10 physical (5 logical) endpoints including one control endpoint.
Single and double buffering supported.
Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
Supports wake-up from Deep-sleep mode and Power-down mode on USB activity
and remote wake-up.
Supports SoftConnect.
Supports Link Power Management (LPM).
7.10 USART
The LPC1315/16/17/45/46/47 contains one USART.
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