參數(shù)資料
型號: LPC2158FBD100
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 16-bit-32-bit microcontrollers; 512 kB flash, with 32 segment x 4 LCD driver
中文描述: 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁數(shù): 20/45頁
文件大小: 220K
代理商: LPC2158FBD100
LPC2157_2158_2
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 9 February 2009
20 of 45
NXP Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
6.12 I
2
C-bus serial I/O controller
The LPC2157/2158 each contain two I
2
C-bus controllers.
The I
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2157/2158 supports bit rates up to 400 kbit/s (Fast
I
2
C-bus).
6.12.1
Features
Compliant with standard I
2
C-bus interface.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus can be used for test and diagnostic purposes.
6.13 SPI serial I/O controller
The LPC2157/2158 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
6.13.1
Features
Compliant with SPI specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
6.14 SSP serial I/O controller
The LPC2157/2158 each contain one Serial Synchronous Port controller (SSP). The SSP
controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact
with multiple masters and slaves on the bus. However, only a single master and a single
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