參數(shù)資料
型號(hào)： LPC2214FBD144
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： Single-chip 16-32-bit ARM microcontrollers; 128-256 kB ISP-IAP flash with 10-bit ADC and external memory interface
封裝： LPC2212FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2214FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486
文件頁(yè)數(shù)： 23/47頁(yè)
文件大?。?/td> 337K
代理商： LPC2214FBD144
LPC2212_2214
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
23 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
DD
ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.18.4
Code security (Code Read Protection - CRP)
This feature of the LPC2212/2214 allows the user to enable different levels of security in
the system so that access to the on-chip flash and use of the JTAG and ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
Remark:
Devices without the suffix /00 or /01 have only a security level equivalent to
CRP2 available.
6.18.5
External interrupt inputs
The LPC2212/2214 include up to nine edge or level sensitive External Interrupt Inputs as
selectable pin functions. When the pins are combined, external events can be processed
as four independent interrupt signals. The External Interrupt Inputs can optionally be used
to wake up the processor from Power-down mode.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LPC2214FBD144,551 功能描述:ARM微控制器 - MCU PREF PART LPC2214FBD144/01-S RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LPC2214FBD144,557 制造商:NXP Semiconductors 功能描述:IC,MCU ARM7, 144LQFP
LPC2214FBD144/00 制造商:NXP Semiconductors 功能描述:16/32BIT ARM7 MCU 128K FLASH SMD
LPC2214FBD144/00,5 制造商:NXP Semiconductors 功能描述:MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC 256KB Flash 1.8V/3.3V 144-Pin LQFP Tray
LPC2214FBD144/00,551 制造商:NXP 功能描述:0
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