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參數(shù)資料
| 型號： | LPC2290FBD144 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | 16-32-bit ARM microcontroller with CAN, 10-bit ADC and external memory interface |
| 封裝： | LPC2290FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,; |
| 文件頁數(shù)： | 19/41頁 |
| 文件大?。?/td> | 198K |
| 代理商： | LPC2290FBD144 |
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LPC2290_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 16 November 2006
19 of 41
NXP Semiconductors
LPC2290
16/32-bit ARM microcontroller with external memory interface
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in baud rate generator.
Standard modem interface signals included on UART1.
6.10.2
UART features available in LPC2290/01 only
The transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs and hardware (CTS/RTS) flow control on UART1 only.
Fractional baud rate generator enables standard baud rates such as 115200 to be
achieved with any crystal frequency above 2 MHz.
Auto-bauding.
Auto-CTS/RTS flow-control fully implemented in hardware.
6.11 I
2
C-bus serial I/O controller
The I
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2290 supports bit rate up to 400 kbit/s (Fast I
2
C-bus).
6.11.1
Features
Compliant with standard I
2
C-bus interface.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus may be used for test and diagnostic purposes.
6.12 SPI serial I/O controller
The LPC2290 contains two SPIs. The SPI is a full duplex serial interface, designed to be
able to handle multiple masters and slaves connected to a given bus. Only a single master
and a single slave can communicate on the interface during a given data transfer. During a
data transfer the master always sends a byte of data to the slave, and the slave always
sends a byte of data to the master.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LPC2290FBD144,551 | 功能描述:ARM微控制器 - MCU RLESS/16K RM/2 CAN/ADC/EXT BUS RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC2290FBD144/01 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16/32-bit ARM microcontroller with CAN, 10-bit ADC and external memory interface |
| LPC2290FBD144/01,5 | 功能描述:ARM微控制器 - MCU ARM7 16KR/2CAN/ADC ROMLESS RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC2290FBD144551 | 制造商:NXP Semiconductors 功能描述:IC 16/32BIT MCU ARM7 SMD LPC2290 |
| LPC2292 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface |
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