參數(shù)資料
型號(hào): LPC2292FBD144,551
廠商: NXP Semiconductors
文件頁(yè)數(shù): 5/54頁(yè)
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 256K 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: LPC2200
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 60MHz
連通性: CAN,EBI/EMI,I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 112
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
配用: OM10091-ND - KIT DEV PHYCORE-ARM7/LPC2220
568-1757-ND - BOARD EVAL FOR LPC220X ARM MCU
其它名稱: 568-1230
935275656551
LPC2292FBD144-S
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
13 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
P3[17]/A17
N5[7]
O
A17 — External memory address line 17.
P3[18]/A18
M5[7]
O
A18 — External memory address line 18.
P3[19]/A19
O
A19 — External memory address line 19.
P3[20]/A20
K5[7]
O
A20 — External memory address line 20.
P3[21]/A21
N4[7]
O
A21 — External memory address line 21.
P3[22]/A22
K4[7]
O
A22 — External memory address line 22.
P3[23]/A23/
XCLK
N3[7]
I/O
A23 — External memory address line 23.
O
XCLK — Clock output.
P3[24]/CS3
M2[7]
O
CS3 — LOW-active Chip Select 3 signal.
(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)
P3[25]/CS2
M1[7]
O
CS2 — LOW-active Chip Select 2 signal.
(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)
P3[26]/CS1
K2[7]
O
CS1 — LOW-active Chip Select 1 signal.
(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)
P3[27]/WE
K1[7]
O
WE — LOW-active Write enable signal.
P3[28]/BLS3/
AIN7
J4[6]
O
BLS3 — LOW-active Byte Lane Select signal (Bank 3).
I
AIN7 — ADC, input 7. This analog input is always connected
to its pin.
P3[29]/BLS2/
AIN6
J3[6]
O
BLS2 — LOW-active Byte Lane Select signal (Bank 2).
I
AIN6 — ADC, input 6. This analog input is always connected
to its pin.
P3[30]/BLS1
O
BLS1 — LOW-active Byte Lane Select signal (Bank 1).
P3[31]/BLS0
F10[7]
O
BLS0 — LOW-active Byte Lane Select signal (Bank 0).
TD1
H2[7]
O
TD1: CAN1 transmitter output.
RESET
135[8]
C5[8]
I
External Reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
XTAL1
142[9]
C3[9]
I
Input to the oscillator circuit and internal clock generator
circuits.
XTAL2
141[9]
B3[9]
O
Output from the oscillator amplifier.
VSS
3, 9, 26, 38,
54, 67, 79,
93, 103, 107,
111, 128
C2, E4, J2,
N2, N7, L10,
K12, F13,
D11, B13,
B11, D7
I
Ground: 0 V reference.
VSSA
139
C4
I
Analog ground: 0 V reference. This should nominally be the
same voltage as VSS, but should be isolated to minimize noise
and error.
VSSA(PLL)
138
B4
I
PLL analog ground: 0 V reference. This should nominally be
the same voltage as VSS, but should be isolated to minimize
noise and error.
VDD(1V8)
37, 110
N1, A12
I
1.8 V core power supply: This is the power supply voltage
for internal circuitry.
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
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