參數(shù)資料
型號: LPC2294HBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: 16-32-bit ARM microcontrollers; 256 kB ISP-IAP flash with CAN, 10-bit ADC and external memory interface
封裝: LPC2292FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2292FET144/01<SOT569-1 (TFBGA144)|<<http://www.nxp.com/packages/SOT56
文件頁數(shù): 44/54頁
文件大小: 428K
代理商: LPC2294HBD144
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
44 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
Table 12.
C
L
= 25 pF, T
amb
= 40
C
Symbol
Parameter
Common to read and write cycles
t
CHAV
XCLK HIGH to address valid
time
t
CHCSL
XCLK HIGH to CS LOW time
t
CHCSH
XCLK HIGH to CS HIGH
time
t
CHANV
XCLK HIGH to address
invalid time
Read cycle parameters
t
CSLAV
CS LOW to address valid
time
t
OELAV
OE LOW to address valid
time
t
CSLOEL
CS LOW to OE LOW time
t
am
memory access time
External memory interface dynamic characteristics
Conditions
Min
Typ Max
Unit
-
-
10
ns
-
-
-
-
10
10
ns
ns
-
-
10
ns
[1]
5
-
+10
ns
[1]
5
-
+10
ns
5
-
-
+5
-
ns
ns
[2][3]
(T
cy(CCLK)
(2 + WST1)) +
(
20)
t
am(ibr)
memory access time (initial
burst-ROM)
memory access time
(subsequent burst-ROM)
data input hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
XCLK HIGH to OE LOW time
XCLK HIGH to OE HIGH
time
Write cycle parameters
t
AVCSL
address valid to CS LOW
time
t
CSLDV
CS LOW to data valid time
t
CSLWEL
CS LOW to WE LOW time
t
CSLBLSL
CS LOW to BLS LOW time
t
WELDV
WE LOW to data valid time
t
CSLDV
CS LOW to data valid time
t
WELWEH
WE LOW to WE HIGH time
[2][3]
(T
cy(CCLK)
(2 + WST1)) +
(
20)
-
-
ns
t
am(sbr)
[2][4]
T
cy(CCLK)
+ (
20)
-
-
ns
t
h(D)
t
CSHOEH
t
OEHANV
[5]
0
-
-
-
-
+5
+5
ns
ns
ns
5
5
t
CHOEL
t
CHOEH
5
5
-
-
+5
+5
ns
ns
[1]
T
cy(CCLK)
10
-
-
ns
5
5
5
5
5
-
-
-
-
-
-
+5
+5
+5
+5
+5
T
cy(CCLK)
(1 +
WST2) + 5
T
cy(CCLK)
(1 + WST2) + 5
T
cy(CCLK)
+ 5
ns
ns
ns
ns
ns
ns
[2]
T
cy(CCLK)
(1 + WST2)
5
t
BLSLBLSH
BLS LOW to BLS HIGH time
[2]
T
cy(CCLK)
(1 + WST2)
5
-
ns
t
WEHANV
WE HIGH to address invalid
time
WE HIGH to data invalid time
BLS HIGH to address invalid
time
[2]
T
cy(CCLK)
5
-
ns
t
WEHDNV
t
BLSHANV
[2]
(2
T
cy(CCLK)
)
5
[2]
T
cy(CCLK)
5
-
-
(2
T
cy(CCLK)
) + 5
T
cy(CCLK)
+ 5
ns
ns
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