參數(shù)資料
型號: LPC2377FBD144
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 16-bit-32-bit microcontrollers; 512 kB flash with ISP-IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC-DAC
中文描述: 32-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù): 20/68頁
文件大小: 1443K
代理商: LPC2377FBD144
LPC2377_78
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 17 June 2010
20 of 68
NXP Semiconductors
LPC2377/78
Single-chip 16-bit/32-bit microcontrollers
7.7.1
Features
Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode
Low transaction latency
Read and write buffers to reduce latency and to improve performance
8 data and 16 address lines wide static memory support
Two chip selects for static memory devices
Static memory features include:
Asynchronous page mode read
Programmable Wait States (WST)
Bus turnaround delay
Output enable and write enable delays
Extended wait
7.8 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2377/78
peripherals to have DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
7.8.1
Features
Two DMA channels. Each channel can support a unidirectional transfer.
The GPDMA can transfer data between the 8 kB SRAM and peripherals such as the
SD/MMC, two SSP, and I
2
S-bus interfaces.
Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time, the channel with the
highest priority is serviced first.
AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.
One AHB master for transferring data. This interface transfers data when a DMA
request goes active.
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