參數(shù)資料
型號： LPC2478FBD208
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學處理器
英文描述： Single-chip 16-bit-32-bit micro; 512 kB flash, Ethernet, CAN, LCD, USB 2.0 device-host-OTG, external memory interface
封裝： LPC2478FBD208<SOT459-1 (LQFP208)|<<http://www.nxp.com/packages/SOT459-1.html<1<Always Pb-free,;LPC2478FET208<SOT950-1 (TFBGA208)|<<http://www.nxp.com/packages/SOT950-1.ht
文件頁數(shù)： 64/93頁
文件大小： 751K
代理商： LPC2478FBD208
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11.5 Static external memory interface
L
A
P
R
6
N
L
S
Table 15.
C
L
= 30 pF, T
amb
=
40
C to 85
C, V
DD(DCDC)(3V3)
= V
DD(3V3)
= 3.0 V to 3.6 V
Symbol
Parameter
Common to read and write cycles
[1]
t
CSLAV
CS LOW to address valid
time
Read cycle parameters
[1][2]
t
OELAV
OE LOW to address valid
time
t
CSLOEL
CS LOW to OE LOW time
t
am
memory access time
Dynamic characteristics: Static external memory interface
Conditions
Min
Typ
Max
Unit
0.29
0.20
2.54
ns
0.29
0.20
2.54
ns
0.78 + T
cy(CCLK)
WAITOEN 0 + T
cy(CCLK)
WAITOEN
[3][4]
(WAITRD
WAITOEN + 1)
T
cy(CCLK)
12.70
[5]
0
0.49
0.20
0.49 + T
cy(CCLK)
WAITOEN
(WAITRD
WAITOEN + 1)
T
cy(CCLK)
8.11
-
0.20
2.44
ns
ns
(WAITRD
WAITOEN + 1)
T
cy(CCLK)
9.57
-
0
0.20
t
h(D)
t
CSHOEH
t
OEHANV
data input hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
OE LOW to OE HIGH time
ns
ns
ns
t
OELOEH
0.59 + (WAITRD
WAITOEN + 1)
T
cy(CCLK)
0.39
0 + (WAITRD
WAITOEN +
1)
T
cy(CCLK)
0
0.10 + (WAITRD
WAITOEN + 1)
T
cy(CCLK)
2.54
t
BLSLAV
BLS LOW to address valid
time
CS HIGH to BLS HIGH time
Write cycle parameters
[1][6]
t
CSLWEL
CS LOW to WE LOW time
ns
t
CSHBLSH
0.88
0.49
0.68
ns
0.88 + T
cy(CCLK)
(1 +
WAITWEN)
0.88
0.68
0
0.10 + T
cy(CCLK)
(1 +
WAITWEN)
0.49
2.54
2.64
0 + T
cy(CCLK)
(WAITWR
WAITWEN + 1)
0 + T
cy(CCLK)
(WAITWR
WAITWEN + 3)
0.20 + T
cy(CCLK)
0.20 + T
cy(CCLK)
(1 +
WAITWEN)
0.98
5.86
4.79
0.10 + T
cy(CCLK)
(WAITWR
WAITWEN + 1)
0.59 + T
cy(CCLK)
(WAITWR
WAITWEN + 3)
2.74 + T
cy(CCLK)
ns
t
CSLBLSL
t
WELDV
t
CSLDV
t
WELWEH
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
ns
ns
ns
ns
[3]
0.78 + T
cy(CCLK)
(WAITWR
WAITWEN + 1)
t
BLSLBLSH
BLS LOW to BLS HIGH
time
t
WEHANV
WE HIGH to address invalid
time
[3]
0.88 + T
cy(CCLK)
(WAITWR
WAITWEN + 3)
ns
[3]
0 + T
cy(CCLK)
ns
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