參數(shù)資料
型號： LPC2929FBD144
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù)： 23/95頁
文件大小： 1855K
代理商： LPC2929FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
23 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
Remark:
If the programmed number of wait-states is more than three, flash-data reading
cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative
reading is active.
6.8.6
EEPROM
EEPROM is a non-volatile memory mostly used for storing relatively small amounts of
data, for example for storing settings. It contains one 16 kB memory block and is
byte-programmable and byte-erasable.
The EEPROM can be accessed only through the flash controller.
6.9 External static memory controller
The LPC2926/2927/2929 contains an external Static Memory Controller (SMC) which
provides an interface for external (off-chip) memory devices.
Key features are:
Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and
external I/O devices
Asynchronous page-mode read operation in non-clocked memory subsystems
Asynchronous burst-mode read access to burst-mode ROM devices
Independent configuration for up to eight banks, each up to 16 MB
Programmable bus-turnaround (idle) cycles (one to 16)
Programmable read and write wait states (up to 32), for static RAM devices
Programmable initial and subsequent burst-read wait state for burst-ROM devices
Programmable write protection
Programmable burst-mode operation
Programmable external data width: 8 bits, 16 bits or 32 bits
Programmable read-byte lane enable control
6.9.1
Description
The SMC simultaneously supports up to eight independently configurable memory banks.
Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting
SRAM, ROM, burst-ROM memory, or external I/O devices.
A separate chip select output is available for each bank. The chip select lines are
configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory
addressing.
Table 11
shows how the 32-bit system address is mapped to the external bus
memory base addresses, chip selects, and bank internal addresses.
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