參數(shù)資料
型號: LPC3220FET296/01,5
廠商: NXP Semiconductors
文件頁數(shù): 35/57頁
文件大小: 0K
描述: IC ARM9 MCU 128K 296-TFBGA
標準包裝: 126
系列: LPC3200
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 266MHz
連通性: EBI/EMI,I²C,IrDA,Microwire,SPI,SSI,SSP,UART/USART,USB OTG
外圍設備: DMA,I²S,電機控制 PWM,PWM,WDT
輸入/輸出數(shù): 51
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 3x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 296-TFBGA
包裝: 托盤
其它名稱: 568-4965
935290763551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
40 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.9 Other peripherals
In addition to the communication peripherals there are many general purpose peripherals
available in the LPC3220/30/40/50. Here is a list of the general purpose peripherals.
GPI/O
Keyboard scanner
Touch screen controller and 10-bit Analog-to-Digital-Converter
Real-time clock
High-speed timer
Four general purpose 32-bit timer/external event counters
Two simple PWMs
One motor control PWM
A short functional description of each of these peripherals is provided in the following
sections.
7.9.1 General purpose parallel I/O
Some device pins that are not dedicated to a specific peripheral function have been
designed to be general purpose inputs, outputs, or input/outputs. Also, some pins may be
configured either as a specific peripheral function or a general purpose input, output, or
input/output. A total of 51 pins can potentially be used as general purpose input/outputs,
24 as general purpose outputs, and 22 as general purpose inputs.
GPIO pins may be dynamically configured as inputs or outputs. Separate registers allow
setting or clearing any number of GPIO and GPO outputs controlled by that register
simultaneously. The value of the output register for standard GPIOs and GPO pins may
be read back, as well as the current actual state of the port pins.
In addition to GPIO pins on port 0, port 1, and port 2, there are 22 GPI, 24 GPO, and
six GPIO pins. When the SDRAM bus is configured for 16 data bits, 13 of the remaining
SDRAM data pins may be used as GPIOs.
7.9.1.1
Features
Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
A single register selects direction for pins that support both input and output modes.
Direction control of individual bits.
For input/output pins, both the programmed output state and the actual pin state can
be read.
There are a total of 12 general purpose inputs, 24 general purpose outputs, and six
general purpose input/outputs.
Additionally, 13 SDRAM data lines may be used as GPIOs if a 16-bit SDRAM
interface is used (rather than a 32-bit interface).
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