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參數(shù)資料
| 型號： | LPC47M112 |
| 廠商： | SMSC Corporation |
| 英文描述： | ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE |
| 中文描述： | 增強(qiáng)的超級I / O控制器，LPC接口 |
| 文件頁數(shù)： | 54/228頁 |
| 文件大?。?/td> | 1269K |
| 代理商： | LPC47M112 |
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7.4.4 DATA TRANSFER COMMANDS
All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same
results information, the only difference being the coding of bits 0-4 in the first byte.
An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely
transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek
portion of the command. If the seek portion fails, it is reflected in the results status normally returned for a
Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder
on which the seek failed.
SMSC DS – LPC47M192
Page 54
Rev. 03/30/05
DATASHEET
Read Data
A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been
issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the
Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the
diskette matches with the sector address specified in the command, the FDC reads the sector’s data field and
transfers the data to the FIFO.
After completion of the read operation from the current sector, the sector address is incremented by one and the data
from the next logical sector is read and output via the FIFO. This continuous read function is called “Multi-Sector
Read Operation”. Upon receipt of the TC cycle, or an implied TC (FIFO overrun/underrun), the FDC stops sending
data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector,
terminate the Read Data Command.
N determines the number of bytes per sector (see Table 18 below). If N is set to zero, the sector size is set to 128.
The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the
specified number of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for CRC
errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to
FF Hex and has no impact on the number of bytes transferred.
Table 18 – Sector Sizes
N
00
01
02
03
..
07
SECTOR SIZE
128 bytes
256 bytes
512 bytes
1024 bytes
…
16 Kbytes
The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N
(number of bytes/sector).
The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder,
data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1.
If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon
the state of the MT bit and EOT byte. Refer to Table 19.
At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval
(specified in the Specify command) has elapsed. If the host issues another command before the head unloads,
then the head settling time may be saved between subsequent reads.
If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette’s
index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to
“01” indicating abnormal termination, sets the ND bit in Status Register 1 to “1” indicating a sector not found, and
terminates the Read Data Command.
After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID
or data field, the FDC sets the IC code in Status Register 0 to “01” indicating abnormal termination, sets the DE bit
flag in Status Register 1 to “1”, sets the DD bit in Status Register 2 to “1” if CRC is incorrect in the ID field, and
terminates the Read Data Command. Table 20 describes the effect of the SK bit on the Read Data command
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LPC47M112_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:Enhanced Super I/O Controller with LPC Interface |
| LPC47M112-MC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| LPC47M112-MW | 功能描述:以太網(wǎng) IC Enhanced Super I/O Cntrl LPC Interface RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47M133-NC | 制造商:SMSC 功能描述: |
| LPC47M140-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
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