- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358934 > LPC47M14V-NC (SMSC Corporation) AT PRINTER SERIAL CBL DB9 FEMALE - DB25 MALE PDF資料下載
參數(shù)資料
| 型號： | LPC47M14V-NC |
| 廠商： | SMSC Corporation |
| 英文描述： | AT PRINTER SERIAL CBL DB9 FEMALE - DB25 MALE |
| 中文描述： | 128引腳ENGANCED超級I / O與LPC接口和USB集線器控制器 |
| 文件頁數(shù)： | 80/205頁 |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14V-NC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁當(dāng)前第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁
SMSC DS – LPC47M14X
Page 80
Rev. 03/19/2001
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a
logic 0 indicates the presence of paper.
BIT 6 nACK - ACKNOWLEDGE
The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer
has received a character and can now accept another. A logic 1 means that it is still processing the last character or has
not received the data.
BIT 7 nBUSY - nBUSY
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in
this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the
next character.
CONTROL PORT
ADDRESS OFFSET = 02H
The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized by the RESET
input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the nSTROBE output.
This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each
line is printed. A logic 0 means no autofeed.
BIT 2 nINIT - INITIATE OUTPUT
This bit is output onto the nINIT output without inversion.
BIT 3 SLCTIN - PRINTER SELECT INPUT
This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the
printer is not selected.
BIT 4 IRQE - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port
to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is
programmed low the IRQ is disabled.
BIT 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state
of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1
means that the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
EPP ADDRESS PORT
ADDRESS OFFSET = 03H
The EPP Address Port is located at an offset of '03H' from the base address. The address register is cleared at
initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non
inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP ADDRESS WRITE cycle to be
performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 -
PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data
output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register
is only available in EPP mode.
EPP DATA PORT 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at initialization
by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and
output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during
which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read.
An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the
deassertion of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP
mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC47M14R-NC | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14I-NC | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14K-NC | RESTR 1.50K 1 TOL 1/8W MF |
| LPC47M14P-NC | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14X | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC47M14W-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14X | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14X-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14Y-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14Z-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。