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參數(shù)資料
| 型號(hào)： | LPC47N217-JV |
| 廠商： | SMSC Corporation |
| 英文描述： | 64 - PIN SUPUR I/O WITH LPC INTERFACE |
| 中文描述： | 64 -針蘇布爾的I / LPC接口? |
| 文件頁(yè)數(shù)： | 92/228頁(yè) |
| 文件大?。?/td> | 1269K |
| 代理商： | LPC47N217-JV |
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BIT 7 nBusy
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register.
SMSC DS – LPC47M192
Page 92
Rev. 03/30/05
DATASHEET
DEVICE CONTROL REGISTER (dcr)
ADDRESS OFFSET = 02H
The Control Register is located at an offset of ‘02H’ from the base address. The Control Register is initialized to zero
by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the nSTROBE output.
BIT 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each
line is printed. A logic 0 means no autofeed.
BIT 2 nINIT - INITIATE OUTPUT
This bit is output onto the nINIT output without inversion.
BIT 3 SELECTIN
This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the
printer is not selected.
BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the
Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt
under Operation, Interrupts.
BIT 5 DIRECTION
If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In
all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means
that the printer port is in input mode (read).
BITS 6 and 7 during a read are a low level, and cannot be written.
cFifo (Parallel Port Data FIFO)
ADDRESS OFFSET = 400h
Mode = 010
Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral
using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the
forward direction.
ecpDFifo (ECP Data FIFO)
ADDRESS OFFSET = 400H
Mode = 011
Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware
handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned.
Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the
direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC47N217N | 制造商:SMSC 制造商全稱:SMSC 功能描述:64-Pin Super I/O with LPC Interface |
| LPC47N217N-ABZJ | 功能描述:輸入/輸出控制器接口集成電路 3.3volts 5V tolerant RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47N217N-ABZJ-TR | 功能描述:接口 - 專用 56 Pin Super I/O LPC Interface RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| LPC47N217N-JV | 制造商:SMSC 制造商全稱:SMSC 功能描述:64-Pin Super I/O with LPC Interface |
| LPC47N227 | 制造商:SMSC 制造商全稱:SMSC 功能描述:100 Pin Super I/O with LPC Interface for Notebook Applications |
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