參數資料
型號: LRI64-A7T
廠商: 意法半導體
英文描述: Memory TAG IC, 64-bit Unique ID with WORM User Area 13.56MHz, ISO 15693 Standard Compliant
中文描述: 內存標簽IC,64位唯一ID與WORM的用戶區(qū)13.56,ISO 15693標準兼容
文件頁數: 11/38頁
文件大?。?/td> 515K
代理商: LRI64-A7T
11/38
LRI64
COMMUNICATIONS SIGNAL FROM LRI64 TO VCD
The ISO15693 standard defines several modes,
for some parameters, to cater for use in different
application requirements and noise environments.
The LRI64 does not support all of these modes,
but supports the single subcarrier mode at the fast
data rate.
Load Modulation
The LRI64 is capable of communication to the
VCD via the inductive coupling between the two
antennas. The carrier is loaded, with a subcarrier
with frequency
f
S
, generated by switching a load in
the LRI64.
The amplitude of the variation to the signal, as re-
ceived on the VCD antenna, is at least 10mV,
when measured as described in the test methods
defined in International Standard ISO10373-7.
Subcarrier
The LRI64 supports the one subcarrier modulation
response format. This format is selected by the
VCD using the first bit in the protocol header.
The frequency,
f
S
, of the subcarrier load modula-
tion is 423.75kHz (=
f
C
/32).
Data Rate
The LRI64 response uses the high data rate for-
mat (26.48 kbits/s). The selection of the data rate
is made by the VCD using the second bit in the
protocol header.
Bit Representation and Coding using One
Subcarrier, at the High Data Rate
Data bits are encoded using Manchester coding,
as described in
Figure 9.
and
Figure 10.
Logic 0.
A logic 0 starts with 8 pulses of
423.75kHz (
f
C
/32) followed by an unmodulated
period of 18.88μs as shown in
Figure 9.
Figure 9. Logic 0, High Data Rate
Logic 1.
A logic 1 starts with an unmodulated
period of 18.88μs followed by 8 pulses of
423.75kHz (
f
C
/32) as shown in
Figure 10.
Figure 10. Logic 1, High Data Rate
AI06663
37.76 μs
AI06664
37.76 μs
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