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參數(shù)資料
| 型號(hào)： | LS5912 |
| 廠商： | Linear Integrated Systems |
| 英文描述： | IMPROVED LOW NOISE WIDEBAND MONOLITHIC DUAL N-CHANNEL JFET |
| 中文描述： | 低噪聲寬頻帶改進(jìn)整體式雙N溝道結(jié)型場(chǎng)效應(yīng)管 |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大?。?/td> | 337K |
| 代理商： | LS5912 |
Linear Integrated Systems
4042 Clipper Court Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
DYNAMIC ELECTRICAL CHARACTERISTICS @25 °C (unless otherwise stated)
LS5911
MIN MAX
LS5912
MIN MAX
LS5912C
MIN MAX
SYM.
CHARACTERISTIC
TYP
UNIT
CONDITIONS
f
= 1kHz
4000 10000 4000 10000 4000 10000
g
fs
Forward
Transconductance
f
= 100MHz
4000 10000 4000 10000 4000 10000
f
= 1kHz
100
100
100
g
os
Output Conductance
f
= 100MHz
150
150
150
μS
V
DG
= 10V, I
D
= 5mA
C
iss
C
rss
Input Capacitance
Reverse Transfer Capacitance
5
5
5
1.2
1.2
1.2
pF
V
DG
= 10V, I
D
= 5mA
f
= 1MHz
NF
Noise Figure
1
1
1
dB
V
DG
= 10V, I
D
= 5mA
f
= 10kHz, R
G
= 100K
V
DG
= 10V, I
D
= 5mA
f
= 100Hz
V
DG
= 10V, I
D
= 5mA
f
= 10kHz
f
= 100Hz
7
20
20
20
nV/
√
Hz
e
n
Equivalent Input
Noise Voltage
f
= 10kHz
4
10
10
10
nV/
√
Hz
1.
2.
3.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implicatio
otherwise under any patent or patent rights of Linear Integrated Systems.
Absolute maximum ratings are limiting values above which serviceability may be impaired.
Pulse Test: PW
≤
300μs Duty Cycle
≤
3%
Assumes smaller value in numerator.
n or
1
2
3
4
8
7
6
5
SOIC-B
S1
D1
G1
NC
NC
G2
D2
S2
1
2
3
4
8
7
6
5
PDIP-B
S1
D1
G1
NC
NC
G2
D2
S2
Please contact the factory
regarding the availability of
optional packages.
TO-78
0.335
0.370
0.305
0.335
0.016
DIM. A
0.165
0.185
0.040
0.016
DIM. B
MIN. 0.500
0.200
0.100
0.100
0.028
0.034
45°
1
2 3
5
6
7
0.029
0.045
SEATING
PLANE
1
3
5
SOT-23
DIMENSIONS IN
2
4
6
0.95
1.90
1.50
1.75
2.60
0.35
0.50
2.80
3.00
0.90
1.30
0.00
0.09
0.20
0.10
1
2
3
4
8
7
6
5
PDIP-A
S1
D1
SS
G1
G2
SS
D2
S2
1
2
3
4
8
7
6
5
SOIC-A
S1
D1
SS
G1
G2
SS
D2
S2
TO-71
Six Lead
0.230
0.209
DIA.
DIA.
0.195
0.175
0.030
MAX.
0.500 MIN.
0.150
0.115
0.019
0.016
DIA.
6 LEADS
3
2
1
5
6
0.046
0.036
45°
0.048
0.028
0.100
0.050
7
1
SOIC
2
3
4
5
6
7
8
DIMENSIONS IN
INCHES
0.2284
0.2440
0.189
0.196
0.0075
0.0098
0.021
0.014
0.018
0.050
0.0040
0.0098
0.150
0.157
1
PDIP
DIMENSIONS IN
INCHES
2
3
4
5
6
7
8
0.145
0.170
0.060
0.100
0.250
0.375
0.038
0.295
0.320
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LS5912_PDIP | 制造商:MICROSS 制造商全稱:MICROSS 功能描述:N-CHANNEL JFET |
| LS5912_SOIC | 制造商:MICROSS 制造商全稱:MICROSS 功能描述:N-CHANNEL JFET |
| LS5912_SOT-23 | 制造商:MICROSS 制造商全稱:MICROSS 功能描述:N-CHANNEL JFET |
| LS5912_TO-71 | 制造商:MICROSS 制造商全稱:MICROSS 功能描述:N-CHANNEL JFET |
| LS5912C | 制造商:LINEAR 制造商全稱:LINEAR 功能描述:IMPROVED LOW NOISE WIDEBAND MONOLITHIC DUAL N-CHANNEL JFET |
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