- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367589 > LS7211-S Delay Line PDF資料下載
參數(shù)資料
| 型號： | LS7211-S |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 66K |
| 代理商： | LS7211-S |
TRIGGER Input (TRIG, Pin 18)
A transition at the TRIG input causes OUT to switch with or
without delay, depending on the selected mode. The TRIG
input to OUT transition relation is always opposite in po-
larity, with the exception of One-Shot mode. (See Mode
definitions above.) TRIG input has an internal pull-down re-
sistor of about 500K
and is buffered by a Schmitt trigger
to provide input hysterisis.
LS7211 TIME BASE Input (RC/CLOCK, Pin 4)
For LS7211, the basic timing signal is applied at the RC/
CLOCK input. The clock can be provided from either an ex-
ternal source or generated by an internal oscillator by con-
necting an R-C network to this input.
The frequency of oscillation is given by
1/RC
.
Chip-to-
chip oscillation tolerance is ± 5% for a fixed value of RC.
The minimum resistance, R
MIN
= 4000
, V
DD
= + 4V
= 1200
, V
DD
= +10V
= 600
, V
DD
= +18V
The external clock mode is selected by applying a logic low
to the RCS/CLKS input (Pin 5); the internal oscillator mode
is selected by applying a high level to the RCS/CLKS input.
LS7212 TIME BASE Input (XTLI/CLOCK, Pin 4)
For LS7212, the basic timing clock is applied to the XLTI/
CLOCK input from either an external clock source or gener-
ated by an internal crystal oscillator by connecting a crystal
between XTLI/CLOCK input and the XTLO output (Pin 5).
LS7211 TIME BASE SELECT Input (RCS/CLKS, Pin 5)
For LS7211, the external clock operation at Pin 4 is se-
lected by applying a logic low to the RCS/CLKS input. The
internal oscillator option with RC timer at Pin 4 is selected
by applying a logic high at the RCS/CLKS input. RCS/CLKS
input has an internal pull-down resistor of about 500K
.
LS7212 TIME BASE Output (XTLO, Pin 5)
For LS7212, when a crystal is used for generating the time
base oscillation, the crystal is connected between XTLI/
CLOCK and XTLO pins.
PRESCALER SELECT Input (PSCLS, Pin 6)
The PSCLS input is a 3-state input, which selects one of
three prescale factors according to Table 2.
TABLE 2. PRESCALE FACTOR SELECTION
PSCLS Input S (Prescale Factor )
Logic Level LS7211 LS7212
Float
Low
High
1
1
3000
3600
32768
32768x60
Using prescale factors of 3000 and 3600, delays in units of
minutes can be produced from 50Hz and 60Hz line sourc-
es. Prescale factors of 32,768 and 32,768 x 60 can be used
to generate accurate delays in units of seconds and min-
utes, respectively, from a 32KHz watch crystal.
7211-102097-2
TIMER RESET Input (RESET, Pin 7)
When RESET input switches high, any timeout in progress
is aborted and OUT switches high without delay. With RE-
SET high, OUT remains high. When RESET switches low
with TRIG low in any mode, OUT remains high. When RE-
SET switches low with TRIG high in Delayed Operate and
Dual Delay modes, the delay timer is started and OUT
switches low at the end of the delay timeout. When RE-
SET switches low with TRIG high in Delayed Release
mode, OUT switches low without delay. When RESET
switches low with TRIG high in One-Shot mode, OUT re-
mains high. RESET input has an internal pull-down resistor
of about 500K
.
V
SS
(-V, Pin 8)
Supply voltage negative terminal or GND.
DELAY Output (OUT, Pin 9)
Except in One-Shot mode, OUT switches with or without
delay (depending on mode) in inverse relation to the logic
level of the TRIG input. In One-Shot mode, a timed low
level is produced at OUT, in response to a positive transi-
tion of the TRIG input.
WEIGHTING BIT Inputs (WB7 To WB0, Pins 10 - 17)
Inputs WB0 through WB7 are binary weighted delay bits
used to program the delay according to the following
relations:
One-Shot Mode: Pulse width = SW
All other Modes: Delay = SW + .5
Where:
S = Prescale factor (See Table 2)
= Time base frequency at Pin 4
W = WB0 + WB1 + ....... WB7
The weighting factor W is calculated by substituting in the
equation above for W, the weighted values for all the WB
inputs that are at logic high. The weighted values for the
WB inputs are shown in Table 3. Each WB input has an in-
ternal pull-down resistor of about 500K
.
TABLE 3. BIT WEIGHTS
BITS
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
VALUE
1
2
4
8
16
32
64
128
V
DD
(+V, Pin 3)
Supply voltage positive terminal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LS7212-S | Delay Line |
| LSA1504 | ASIC |
| LSA1501 | ASIC |
| LSA1502 | ASIC |
| LSA1503 | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LS7212 | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
| LS7212N | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
| LS7212-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| LS7213 | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
| LS7213R | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。