參數(shù)資料
型號(hào): LS7212-S
英文描述: Delay Line
中文描述: 延遲線
文件頁(yè)數(shù): 4/8頁(yè)
文件大?。?/td> 66K
代理商: LS7212-S
A
1
2
B
TRIG 18
CLOCK/RC/XTLI 4
XTLO(LS7212)
5
5
RCS/CLKS(LS7211)
6
PSCLS
1M
1M
OSC
MUX
3-STATE
DECODER
CLOCK
LATCH
EDGE
DETECT
MODE
REG
CONTROL
LOGIC
LATCH/TIMER
PRESCALER
500K
8
BUF
9
10-17
OUT
WB7-WB0
FIGURE 2. LS7211/LS7212 BLOCK DIAGRAM
500K
500K
500K
500K (8)
3
8
+V
-V (Gnd)
+V
+V
+
V
V
DD
V
SS
7
RESET
500K
ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) (Con’t)
Characteristic
SYMBOL
V
DD
Unit
Condition
Min
Max
Min
Max
Min
Max
Switching Characteristics
(See Fig. 3)
4.0
10.0
18.0
4.0
10.0
18.0
4.0
10.0
18.0
-
-
-
-
-
-
-
-
-
1.3
4.0
6.0
2.3
7.0
11.0
1.2
4.0
7.0
-
-
-
-
-
-
-
-
-
1.0
3.0
4.5
1.8
5.5
8.5
0.93
3.0
5.5
-
-
-
-
-
-
-
-
-
0.76
2.3
3.4
1.3
4.0
6.5
0.7
2.3
4.2
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
RC Oscillator Frequency
f
osc
-
External Clock or
Crystal Oscillator
Frequency
For prescale
factor S = 1 or 3000
or 3600
S = 32768
or
32768 X 60
f
ext
f
ext
TRIG Set-Up Time
A, B Set-Up Time
WB0 - WB7 Set-Up Time
t
1
t
2
t
3
-
-
-
23
0
0
215
80
50
-
-
-
-
-
-
30
0
0
280
105
65
-
-
-
-
-
-
40
0
0
370
140
85
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
-
-
4.0
10.0
18.0
Clock to Out Delay
t
4
C
L
= 50pF
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