參數(shù)資料
型號: LS7566
廠商: LSI Corporation
元件分類: 通用總線功能
英文描述: 24-BIT FOUR-AXES QUADRATURE COUNTER
中文描述: 24位的4軸正交計數(shù)器
文件頁數(shù): 5/13頁
文件大小: 97K
代理商: LS7566
I/O PINS
: The following is a description of the input/out pins.
RSO(
Pin 3)
, RS1
(Pin 2)
, RS2
(Pin1).
Inputs. These three inputs select the hardware registers for read/write access according to Table 1.
TABLE 1
CS/ RS2 RS1 RS0 RD/ WR/ SELECTED REGISTER
1
x
x
x
x
x
x
x
x
0
x
x
x
x
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
OPERATION
none
none
none
READ (see Note 2)
READ
READ
READ
READ
READ
READ
none
WRITE
WRITE
WRITE
none
WRITE
WRITE
WRITE
WRITE
x
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
none
none
none
[ISR:IMR]
MDR0
MDR1
STR
OL0
OL1
OL2
none
IMR
MDR0
MDR1
none
PR0
PR1
PR2
CMR
Note 1
. x indicates don’t care case.
Note 2
. DB0 through DB3 contain IMR B0 through B3; DB4 through DB7 contain ISR B0 through B3.
CHS0
(Pin 5),
CHS1
(Pin 4)
Inputs. These two inputs select one of four axes for read/write access according to the following table.
The registers within the axis are selected according to Table 1.
TABLE 2
CHS1 CHS0 AXIS
0
0
1
1
0
1
0
1
x0
x1
x2
x3
RD/
(Pin 8) Input. A low on RD/ input accesses an ad-
dressed register for read and places the data on the
octal databus, DB<7:0>. The register selection is
made according to Table 1.
CS/
(Pin 9) Input. A low on the CS/ input enables the
chip for read or write operation. When the CS/ input is
high, read and write operations are disabled and the
databus, DB<7:0>, is placed in a high impedance
state.
WR/
(Pin 10) Input. A low pulse on the WR/ input
writes the data on the databus, DB<7:0>, into the ad-
dressed register according to Table 1. The write op-
eration is completed at the trailing edge of the WR/
pulse.
DB<7:0>
(Pin 18 thru Pin 11) Input/Output.
The octal databus, DB<7:0>, is the input/output portal
for write and read data transfers between LS7566 and
the outside world. During a read operation, when both
CS/ and the RD/ inputs are low, DB<7:0> are outputs.
During a write operation, when both CS/ and WR/ are
low, DB<7:0> are inputs. When CS/ is high, DB<7:0>
are in high impedance state independent of the states
of RD/ and WR/.
PCK
(Pin 21) Input. A clock applied at PCK input is
used for validating the logic states of the A and B
quadrature clocks and the INDX input.
The PCK input frequency, f
PCK,
is divided down by a
factor of 1 or 2 according to bit7 of MDR0. The re-
sultant clock is used to sample the logic levels of the
7566-112904-5
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