In the 鈥渙ff鈥� state, I
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� LT1011AIS8#TR
寤犲晢锛� Linear Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 3/20闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC COMPARATOR VOLTAGE 5V 8SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 2,500
椤�(l猫i)鍨嬶細 閫氱敤
鍏冧欢鏁�(sh霉)锛� 1
杓稿嚭椤�(l猫i)鍨嬶細 闁�(k膩i)璺泦闆绘サ
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 3 V ~ 36 V锛�±1.5 V ~ 18 V
闆诲 - 杓稿叆鍋忕Щ锛堟渶灏忓€硷級锛� 0.75mV @ ±15V
闆绘祦 - 杓稿叆鍋忓锛堟渶灏忓€硷級锛� 0.035µA @ ±15V
闆绘祦 - 杓稿嚭锛堟(bi膩o)婧�(zh菙n)锛夛細 50mA
闆绘祦 - 闈滄厠(t脿i)锛堟渶澶у€硷級锛� 4mA
CMRR, PSRR锛堟(bi膩o)婧�(zh菙n)锛夛細 115dB CMRR
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
鍖呰锛� 甯跺嵎 (TR)
LT1011/LT1011A
11
1011afe
For more information www.linear.com/LT1011
applicaTions inForMaTion
In the 鈥渙ff鈥� state, I1 is switched off and both Q1 and Q2
turn off. The collector of Q2 can be now held at any voltage
above V鈥� without conducting current, including voltages
above the positive supply level. Maximum voltage above
V鈥� is 50V for the LT1011M and 40V for the LT1011C/I.
The emitter can be held at any voltage between V+ and
V鈥� as long as it is negative with respect to the collector.
In the 鈥渙n鈥� state, I1 is connected, turning on Q1 and Q2.
DiodesD1andD2preventdeepsaturationofQ2toimprove
speed and also limit the drive current of Q1. The R1/R2
dividersetsthesaturationvoltageofQ2andprovidesturn-
off drive. Either the collector or emitter pin can be held at
a voltage between V+ and V鈥�. This allows the remaining
pin to drive the load. In typical applications, the emitter is
connected to V鈥� or ground and the collector drives a load
tied to V+ or a separate positive supply.
When the emitter is used as the output, the collector is
typically tied to V+ and the load is connected to ground
or V鈥�. Note that the emitter output is phase reversed with
respect to the collector output so that the 鈥�+鈥� and 鈥溾€撯€�
input designations must be reversed. When the collector
Typical applicaTions
Offset Balancing
Driving Load Referenced
to Positive Supply
Driving Load Referenced
to Negative Supply
is tied to V+, the voltage at the emitter in the 鈥渙n鈥� state is
about 2V below V+ (see curves).
Input Signal Range
The common mode input voltage range of the LT1011 is
about300mVabovethenegativesupplyand1.5Vbelowthe
positive supply, independent of the actual supply voltages
(seecurveintheTypicalPerformanceCharacteristics).This
is the voltage range over which the output will respond
correctly when the common mode voltage is applied to
one input and a higher or lower signal is applied to the
remaining input. If one input is inside the common mode
range and one is outside, the output will be correct. If the
inputs are outside the common mode range in opposite
directions, the output will still be correct. If both inputs are
outside the common mode range in the same direction,
the output will not respond to the differential input; for
temperatures of 25掳C and above, the output will remain
unconditionally high (collector output), for temperatures
below 25掳C, the output becomes undefined.
鈥�
+
LT1011
5
R2
3k
R1
20k
6
7
8
2
3
1011 TA03
V+
鈥�
+
LT1011
INPUTS*
2
7
RLOAD
4
1
8
*INPUT POLARITY IS REVERSED
WHEN USING PIN 1 AS OUTPUT
V
V+
3
1011 TA06
鈥�
+
LT1011
3
7
RLOAD
4
1
8
V++ CAN BE GREATER OR LESS THAN V+
V
V+
V++
V
OR
GROUND
2
1011 TA05
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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