參數(shù)資料
型號: LT1016IS8#TR
廠商: Linear Technology
文件頁數(shù): 3/20頁
文件大?。?/td> 0K
描述: IC COMPARATOR 10NS HI SPD 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: UltraFast™
類型: 帶鎖銷
元件數(shù): 1
輸出類型: CMOS,補(bǔ)充型,TTL
電壓 - 輸入偏移(最小值): 3mV @ ±5V
電流 - 輸入偏壓(最小值): 10µA @ ±5V
電流 - 輸出(標(biāo)準(zhǔn)): 20mA
電流 - 靜態(tài)(最大值): 35mA
CMRR, PSRR(標(biāo)準(zhǔn)): 96dB CMRR,75dB PSRR
傳輸延遲(最大): 14ns
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 帶卷 (TR)
LT1016
11
1016fc
applicaTions inForMaTion
“Fuzz” on the edges is the difficulty in Figure 10. This
condition appears similar to Figure 10, but the oscillation
is more stubborn and persists well after the output has
gone low. This condition is due to stray capacitive feed-
back from the outputs to the inputs. A 3k input source
impedance and 3pF of stray feedback allowed this oscil-
lation. The solution for this condition is not too difficult.
Keep source impedances as low as possible, preferably
1k or less. Route output and input pins and components
away from each other.
The opposite of stray-caused oscillations appears in
Figure 11. Here, the output response (Trace B) badly lags
the input (Trace A). This is due to some combination of
high source impedance and stray capacitance to ground
at the input. The resulting RC forces a lagged response
at the input and output delay occurs. An RC combination
of 2k source resistance and 10pF to ground gives a 20ns
time constant—significantly longer than the LT1016’s
responsetime.Keepsourceimpedanceslowandminimize
stray input capacitance to ground.
Figure 12 shows another capacitance related problem.
Here the output does not oscillate, but the transitions
are discontinuous and relatively slow. The villain of this
situation is a large output load capacitance. This could
be caused by cable driving, excessive output lead
length or the input characteristics of the circuit being
driven. In most situations this is undesirable and may be
eliminated by buffering heavy capacitive loads. In a few
circumstances it may not affect overall circuit operation
and is tolerable. Consider the comparator’s output load
characteristics and their potential effect on the circuit. If
necessary, buffer the load.
Figure 11. Stray 5pF Capacitance from
Input to Ground Causes Delay
Figure 12. Excessive Load Capacitance Forces Edge Distortion
Figure 10. 3pF Stray Capacitive Feedback
with 3k Source Can Cause Oscillation
2V/DIV
50ns/DIV
1016 F10
TRACE A
2V/DIV
TRACE B
2V/DIV
10ns/DIV
1016 F11
2V/DIV
100ns/DIV
1016 F12
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