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參數(shù)資料
| 型號： | LT1055CN8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | 13-Input Positive-NAND Gates 16-SOIC 0 to 70 |
| 中文描述： | OP-AMP, 1250 uV OFFSET-MAX, 4.5 MHz BAND WIDTH, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 360K |
| 代理商： | LT1055CN8 |
3
LT1055/LT1056
LT1055AM
LT1056AM
TYP
180
180
1.3
LT1055M
LT1056M
TYP
250
250
1.8
SYMBOL
V
OS
PARAMETER
Input Offset Voltage (Note1)
CONDITIONS
MIN
—
—
—
MAX
500
550
4.0
MIN
—
—
—
MAX
1200
1250
8.0
UNITS
LT1055
LT1056
G
G
μ
V
μ
V
Average Temperature
Coefficient of Input Offset
Voltage
Input Offset Current
(Note 5)
G
μ
V/
°
C
I
OS
Warmed Up
T
A
= 125
°
C
Warmed Up
T
A
= 125
°
C
V
O
=
±
10V, R
L
= 2k
V
CM
=
±
10.5V
V
S
=
±
10V to
±
17V
R
L
= 2k
LT1055
LT1056
LT1055
LT1056
G
G
—
—
—
—
40
85
88
±
12
0.20
0.25
±
0.4
±
0.5
120
100
104
±
12.9
1.2
1.5
±
2.5
±
3.0
—
—
—
—
—
—
—
—
35
82
86
±
12
0.25
0.30
±
0.5
±
0.6
120
98
102
±
12.9
1.8
2.4
±
4.0
±
5.0
—
—
—
—
nA
nA
nA
nA
I
B
Input Bias Current
G
G
A
VOL
CMRR
PSRR
V
OUT
Large-Signal Voltage Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing
G
V/mV
G
dB
dB
V
G
G
ELECTRICAL CHARACTERISTICS
SYMBOL
V
OS
PARAMETER
Input Offset Voltage (Note1)
CONDITIONS
LT1055 H Package
LT1056 H Package
LT1055 N8 Package
LT1056 N8 Package
H Package (Note 5)
N8 Package (Note 5)
MIN
—
—
—
—
—
—
TYP
100
100
—
—
1.2
—
MAX
330
360
—
—
4.0
—
MIN
—
—
—
—
—
—
TYP
140
140
250
280
1.6
3.0
MAX
750
800
1250
1350
8.0
12.0
UNITS
G
G
G
G
μ
V
μ
V
μ
V
μ
V
Average Temperature
Coefficient of Input Offset
Voltage
Input Offset Current
G
G
μ
V/
°
C
μ
V/
°
C
I
OS
Warmed Up
T
A
= 70
°
C
Warmed Up
T
A
= 70
°
C
V
O
=
±
10V, R
L
= 2k
V
Cm
=
±
10.5V
V
S
=
±
10V to
±
18V
R
L
= 2k
LT1055
LT1056
LT1055
LT1056
G
G
—
—
—
—
80
85
89
±
12
10
14
±
30
±
40
250
100
105
±
13.1
50
70
—
—
—
—
60
82
87
±
12
16
18
±
40
±
50
250
98
103
±
13.1
80
100
±
200
±
240
—
—
—
—
pA
pA
pA
pA
I
B
Input Bias Current
G
G
±
150
±
80
—
—
—
—
A
VOL
CMRR
PSRR
V
OUT
Large-Signal Voltage Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing
G
V/mV
G
dB
dB
V
G
G
LT1055AC
LT1056AC
V
S
=
±
15V, V
CM
= 0V, –55
°
C
≤
T
A
≤
125
°
C unless otherwise noted.
The
G
denotes specifications which apply over the full operating
temperature range.
For MIL-STD components, please refer to LTC883 data sheet for test
listing and parameters.
Note 1:
Offset voltage is measured under two different conditions:
(a) approximately 0.5 seconds after application of power; (b) at T
A
= 25
°
C
only, with the chip heated to approximately 38
°
C for the LT1055 and to
45
°
C for the LT1056, to account for chip temperature rise when the device
is fully warmed up.
Note 2:
10Hz noise voltage density is sample tested on every lot of A
grades. Devices 100% tested at 10Hz are available on request.
Note 3:
This parameter is tested on a sample basis only.
Note 4:
Current noise is calculated from the formula: i
n
= (2ql
B
)
1/2
, where
q = 1.6
×
10
–19
coulomb. The noise of source resistors up to 1G
swamps the contribution of current noise.
Note 5: Offset voltage drift with temperature is practically unchanged when
the offset voltage is trimmed to zero with a 100k potentiometer between
the balance terminals and the wiper tied to V
+
. Devices tested to tighter
drift specifications are available on request.
LT1055CH/LT1056CH
LT1055CN8/LT1056CN8
V
S
=
±
15V, V
CM
= 0V, 0
°
C
≤
T
A
≤
70
°
C unless otherwise noted.
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