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參數(shù)資料
| 型號： | LT1056C |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 3-Line to 8-Line Decoders/Demultiplexers With Address Latches 16-SOIC 0 to 70 |
| 中文描述： | 高精度，高速度，JFET輸入運算放大器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 360K |
| 代理商： | LT1056C |
7
LT1055/LT1056
APPLICATIO
S I
N
FOR
ATIO
U
The LT1055/LT1056 may be inserted directly into LF155A/
LT355A, LF156A/LT356A, OP-15 and OP-16 sockets. Off-
set nulling will be compatible with these devices with the
wiper of the potentiometer tied to the positive supply.
W
U
No appreciable change in offset voltage drift with tempera-
ture will occur when the device is nulled with a potentiom-
eter, R
P
, ranging from 10k to 200k.
The LT1055/LT1056 can also be used in LF351, LF411,
AD547, AD611, OPA-111, and TL081 sockets, provided
that the nulling cicuitry is removed. Because of the LT1055/
LT1056’s low offset voltage, nulling will not be necessary
in most applications.
Achieving Picoampere/Microvolt Performance
In order to realize the picoampere-microvolt level accu-
racy of the LT1055/LT1056 proper care must be exer-
cised. For example, leakage currents in circuitry external
to the op amp can significantly degrade performance. High
quality insulation should be used (e.g. Teflon, Kel-F);
cleaning of all insulating surfaces to remove fluxes and
other residues will probably be required. Surface coating
may be necessary to provide a moisture barrier in high
humidity environments.
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs: in inverting configurations the guard
ring should be tied to ground, in noninverting connnections
to the inverting input at pin 2. Guarding both sides of the
printed circuit board is required. Bulk leakage reduction
depends on the guard ring width.
Offset Nulling
The LT1055/LT1056 has the lowest offset voltage of any
JFET input op amp available today. However, the offset
voltage and its drift with time and temperature are still not
as good as on the best bipolar amplifiers because the
transconductance of FETs is considerably lower than that
of bipolar transistors. Conversely, this lower transcon-
ductance is the main cause of the significantly faster
speed performance of FET input op amps.
Offset voltage also changes somewhat with temperature
cycling. The AM grades show a typical 20
μ
V hysteresis
(30
μ
V on the M grades) when cycled over the –55
°
C to
125
°
C temperature range. Temperature cycling from 0
°
C
to 70
°
C has a negligible (less than 10
μ
V) hysteresis
effect.
The offset voltage and drift performance are also affected
by packaging. In the plastic N8 package the molding
compound is in direct contact with the chip, exerting
pressure on the surface. While NPN input transistors are
largely unaffected by this pressure, JFET device matching
and drift are degraded. Consequently, for best DC perfor-
mance, as shown in the typical performance distribution
plots, the TO-5 H package is recommended.
Noise Performance
The current noise of the LT1055/LT1056 is practically
immeasurable at 1.8fA/
√
Hz. At 25
°
C it is negligible up to
1G of source resistance, R
S
(compound to the noise of
R
S
). Even at 125
°
C it is negligible to 100M of R
S
.
LT1055/56 AI2
OFFSET
TRIM
OFFSET
TRIM
N/C
GUARD
OUTPUT
IPT
V
+
V
–
1
8
7
6
5
4
3
2
–
+
V
+
V
–
OUT
2
3
4
1
5
7
R
P
6
LT1055/56 AI1
LT1055
LT1056
Teflon is a trademark of Dupont.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LT1056CH | Precision, High Speed, JFET Input Operational Amplifiers |
| LT1056M | 3-Line to 8-Line Decoders/Demultiplexers With Address Latches 16-PDIP 0 to 70 |
| LT1056MH | 3-Line to 8-Line Decoders/Demultiplexers With Address Latches 16-SO 0 to 70 |
| LT1056S8 | Precision, High Speed, JFET Input Op Amp(精密，高速，結(jié)型場效應(yīng)管輸入單路運算放大器) |
| LT1057AC | 3-Line to 8-Line Decoders/Demultiplexers 16-SOIC 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LT1056CH | 制造商:Linear Technology 功能描述:OP Amp Single GP ±20V 8-Pin TO-5 制造商:Linear Technology 功能描述:OP Amp Single GP 20V 8-Pin TO-5 |
| LT1056CN8 | 功能描述:IC PREC OP-AMP JFET HI-SPD 8-DIP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:通用 電路數(shù):2 輸出類型:滿擺幅 轉(zhuǎn)換速率:1.8 V/µs 增益帶寬積:6.5MHz -3db帶寬:4.5MHz 電流 - 輸入偏壓:5nA 電壓 - 輸入偏移:100µV 電流 - 電源:65µA 電流 - 輸出 / 通道:35mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 5.25 V，±0.9 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:10-MSOP 包裝:管件 |
| LT1056CN8#PBF | 功能描述:IC PREC OP-AMP JFET HI-SPD 8-DIP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 產(chǎn)品培訓(xùn)模塊:Differential Circuit Design Techniques for Communication Applications 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:RF/IF 差分 電路數(shù):1 輸出類型:差分 轉(zhuǎn)換速率:9800 V/µs 增益帶寬積:- -3db帶寬:2.9GHz 電流 - 輸入偏壓:3µA 電壓 - 輸入偏移:- 電流 - 電源:40mA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VQFN 裸露焊盤，CSP 供應(yīng)商設(shè)備封裝:16-LFCSP-VQ 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:551 (CN2011-ZH PDF) 其它名稱:ADL5561ACPZ-R7CT |
| LT1056S8 | 功能描述:IC PREC OP-AMP JFET HI-SPD 8SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:LinCMOS™ 放大器類型:通用 電路數(shù):4 輸出類型:- 轉(zhuǎn)換速率:0.05 V/µs 增益帶寬積:110kHz -3db帶寬:- 電流 - 輸入偏壓:0.7pA 電壓 - 輸入偏移:210µV 電流 - 電源:57µA 電流 - 輸出 / 通道:30mA 電壓 - 電源，單路/雙路(±):3 V ~ 16 V，±1.5 V ~ 8 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:管件 產(chǎn)品目錄頁面:865 (CN2011-ZH PDF) 其它名稱:296-1834296-1834-5 |
| LT1056S8#PBF | 功能描述:IC PREC OP-AMP JFET HI-SPD 8SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:- 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
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