APPLICATIONS INF" />
參數(shù)資料
型號: LT1056S8
廠商: Linear Technology
文件頁數(shù): 2/16頁
文件大小: 0K
描述: IC PREC OP-AMP JFET HI-SPD 8SOIC
標準包裝: 100
放大器類型: J-FET
電路數(shù): 1
轉(zhuǎn)換速率: 14 V/µs
增益帶寬積: 5.5MHz
電流 - 輸入偏壓: 30pA
電壓 - 輸入偏移: 500µV
電流 - 電源: 5mA
電壓 - 電源,單路/雙路(±): ±5 V ~ 18 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SO
包裝: 管件
10
LT1055/LT1056
10556fc
APPLICATIONS INFORMATION
WU
U
The voltage noise spectrum is characterized by a low 1/f
corner in the 20Hz to 30Hz range, significantly lower than
on other competitive JFET input op amps. Of particular
interest is the fact that with any JFET IC amplifier, the
frequency location of the 1/f corner is proportional to the
square root of the internal gate leakage currents and,
therefore, noise doubles every 20
°C. Furthermore, as
illustrated in the noise versus chip temperature curves,
the 0.1Hz to 10Hz peak-to-peak noise is a strong function
of temperature, while wideband noise (f0 = 1kHz) is
practically unaffected by temperature.
Consequently, for optimum low frequency noise, chip
temperature should be minimized. For example, operating
an LT1056 at
±5V supplies or with a 20°C/W case-to-
ambient heat sink reduces 0.1Hz to 10Hz noise from
typically 2.5
VP-P (±15V, free-air) to 1.5VP-P. Similiarly,
the noise of an LT1055 will be 1.8
VP-P typically because
of its lower power dissipation and chip temperature.
High Speed Operation
Settling time is measured in the test circuit shown. This
test configuration has two features which eliminate prob-
lems common to settling time measurments: (1) probe
capacitance is isolated from the “false summing” node,
and (2) it does not require a “flat top” input pulse since the
input pulse is merely used to steer current through the
diode bridges. For more details, please see Application
Note 10.
As with most high speed amplifiers, care should be
taken with supply decoupling, lead dress and component
placement.
When the feedback around the op amp is resistive (RF), a
pole will be created with RF, the source resistance and
capacitance (RS, CS), and the amplifier input capacitance
(CIN ≈ 4pF). In low closed-loop gain configurations and
with RS and RF in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capacitor
(CF) in parallel with RF eliminates this problem. With RS
(CS + CIN) = RFCF, the effect of the feedback pole is
completely removed.
0.01 DISC
+
+
15V
–15V
15k
10k
4.7k
10
F
SOLID
TANTALUM
10
F
SOLID
TANTALUM
10
F
SOLID
TANTALUM
10
F
SOLID TANTALUM
10pF (TYPICAL)
10k
PULSE GEN
INPUT
(5V MIN STEP)
2k
0.01 DISC
50
2W
LT1055
LT1056
AMPLIFIER
UNDER
TEST
AUT OUTPUT
HP5082-8210
HEWLETT
PACKARD
15V
–15V
= 1N4148
–15V
1/2
U440
1/2
U440
50
3
3
100
DC ZERO
2N160
2N5160
2N3866
LT1055/56 AI04
OUTPUT
TO SCOPE
Settling Time Test Circuit
+
RS
RF
CF
CS
CIN
OUTPUT
LT1055/56 AI03
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