參數(shù)資料
型號: LT1113ACN8
廠商: LINEAR TECHNOLOGY CORP
元件分類: 運動控制電子
英文描述: Dual Low Noise, Precision, JFET Input Op Amps
中文描述: DUAL OP-AMP, 2500 uV OFFSET-MAX, 5.6 MHz BAND WIDTH, PDIP8
封裝: 0.300 INCH, PLASTIC, DIP-8
文件頁數(shù): 10/16頁
文件大?。?/td> 244K
代理商: LT1113ACN8
10
LT1113
U
S
A
O
PPLICATI
U
U
The gain therefore is 1 + C
F
/C
S
. For unity gain, C
F
should
equal the transducer capacitance plus the input capaci-
tance of the LT1113 and R
F
should equal R
S
. In the
noninverting mode example, the transducer current is
converted to a change in voltage by the transducer capaci-
tance; this voltage is then buffered by the LT1113 with a
gain of 1 + R1/R2. A DC path is provided by R
S
, which is
either the transducer impedance or an external resistor.
Since R
S
is usually several orders of magnitude greater
than the parallel combination of R1 and R2, R
B
is added to
balance the DC offset caused by the noninverting input
bias current and R
S
. The input bias currents, although
small at room temperature, can create significant errors
over increasing temperature, especially with transducer
resistances of up to 100M or more. The optimum value for
R
B
is determined by equating the thermal noise (4kTR
S
) to
the current noise (2qI
B
) times R
S2
. Solving for R
S
results
in R
B
= R
S
= 2V
T
/I
B
V
kT
q
mV at
26
C
T
=
=
°
25
.
A parallel capacitor, C
B
, is used to cancel the phase shift
caused by the op amp input capacitance and R
B
.
Reduced Power Supply Operation
The LT1113 can be operated from
±
5V supplies for lower
power dissipation resulting in lower I
B
and noise at the
expense of reduced dynamic range. To illustrate this
benefit, let’s look at the following example:
An LT1113CS8 operates at an ambient temperature of
25
°
C with
±
15V supplies, dissipating 318mW of power
(typical supply current = 10.6mA for the dual). The SO-8
package has a
θ
JA
of 190
°
C/W, which results in a die
temperature increase of 60.4
°
C or a room temperature die
operating temperature of 85.4
°
C. At
±
5V supplies, the die
temperature increases by only one third of the previous
amount or 20.1
°
C resulting in a typical die operating
temperature of only 45.1
°
C. A 40 degree reduction of die
temperature is achieved at the expense of a 20V reduction
in dynamic range. If no DC correction resistor is used at
the input, the input referred offset will be the input bias
current at the operating die temperature times the trans-
ducer resistance (refer to Input Bias and Offset Currents vs
Chip Temperature graph in Typical Performance Charac-
teristics section). A 100mV input V
OS
is the result of a 1nA
I
B
(at 85
°
C) dropped across a 100M transducer resis-
tance; at
±
5V supplies, the input offset is only 28mV (I
B
at
45
°
C is 280pA). Careful selection of a DC correction
+
R2
OUTPUT
R
B
C
B
R1
C
S
R
S
C
B
C
S
R
B
= R
S
R
S
> R1
OR R2
TRANSDUCER
+
OUTPUT
C
F
C
B
R
B
C
B
= C
F
C
S
R
B
= R
F
R
S
Q = CV; d
t = I = C
R
F
C
S
R
S
TRANSDUCER
1113 F02
dV
d
t
Figure 2. Noninverting and Inverting Gain Configurations
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