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參數(shù)資料
| 型號： | LT1113CS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PREC OP-AMP JFET DUAL 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 3.9 V/µs |
| 增益帶寬積： | 5.6MHz |
| 電流 - 輸入偏壓： | 320pA |
| 電壓 - 輸入偏移： | 500µV |
| 電流 - 電源： | 5.3mA |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 20 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
10
LT1113
1113fb
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A
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PPLICATI
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I FOR ATIO
The gain therefore is 1 + CF/CS. For unity gain, CF should
equal the transducer capacitance plus the input capaci-
tance of the LT1113 and RF should equal RS. In the
noninverting mode example, the transducer current is
converted to a change in voltage by the transducer capaci-
tance; this voltage is then buffered by the LT1113 with a
gain of 1 + R1/R2. A DC path is provided by RS, which is
either the transducer impedance or an external resistor.
Since RS is usually several orders of magnitude greater
than the parallel combination of R1 and R2, RB is added to
balance the DC offset caused by the noninverting input
bias current and RS. The input bias currents, although
small at room temperature, can create significant errors
over increasing temperature, especially with transducer
resistances of up to 100M or more. The optimum value for
RB is determined by equating the thermal noise (4kTRS) to
the current noise (2qIB) times RS2. Solving for RS results
in RB = RS = 2VT/IB
V
kT
q
mV at
C
T ==
°
26
25
.
A parallel capacitor, CB, is used to cancel the phase shift
caused by the op amp input capacitance and RB.
Reduced Power Supply Operation
The LT1113 can be operated from
±5V supplies for lower
power dissipation resulting in lower IB and noise at the
expense of reduced dynamic range. To illustrate this
benefit, let’s look at the following example:
An LT1113CS8 operates at an ambient temperature of
25
°C with ±15V supplies, dissipating 318mW of power
(typical supply current = 10.6mA for the dual). The SO-8
package has a
θJA of 190°C/W, which results in a die
temperature increase of 60.4
°C or a room temperature die
operating temperature of 85.4
°C. At ±5V supplies, the die
temperature increases by only one third of the previous
amount or 20.1
°C resulting in a typical die operating
temperature of only 45.1
°C. A 40 degree reduction of die
temperature is achieved at the expense of a 20V reduction
in dynamic range. If no DC correction resistor is used at
the input, the input referred offset will be the input bias
current at the operating die temperature times the trans-
ducer resistance (refer to Input Bias and Offset Currents vs
Chip Temperature graph in Typical Performance Charac-
teristics section). A 100mV input VOS is the result of a 1nA
IB (at 85°C) dropped across a 100M transducer resis-
tance; at
±5V supplies, the input offset is only 28mV (IB at
45
°C is 280pA). Careful selection of a DC correction
–
+
R2
OUTPUT
RB
CB
R1
CS
RS
CB CS
RB = RS
RS > R1 OR R2
TRANSDUCER
–
+
OUTPUT
CF
CB
RB
CB = CFCS
RB = RFRS
RF
CS
RS
TRANSDUCER
1113 F02
Q = CV;
dQ
dt
= I = C
dV
dt
Figure 2. Noninverting and Inverting Gain Configurations
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