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參數(shù)資料
| 型號： | LT1114S#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP QUAD PREC LO PWR 16SOIC |
| 標準包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 4 |
| 轉換速率： | 0.3 V/µs |
| 增益帶寬積： | 750kHz |
| 電流 - 輸入偏壓： | 80pA |
| 電壓 - 輸入偏移： | 25µV |
| 電流 - 電源： | 350µA |
| 電壓 - 電源，單路/雙路(±)： | 2 V ~ 40 V，±1 V ~ 20 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SO |
| 包裝： | 帶卷 (TR) |
11
LT1112/LT1114
111214fb
The concepts of common mode and power supply rejec-
tion ratio match (
CMRR and PSRR) are best demon-
strated with a numerical example:
Assume CMRRA = + 1V/V or 120dB,
and CMRRB = + 0.75V/V or 122.5dB,
then
CMRR = 0.25V/V or 132dB;
if CMRRB = – 0.75V/V which is still 122.5dB,
then
CMRR = 1.75V/V or 115dB.
Clearly the LT1112/LT1114, by specifying and guarantee-
ing all of these matching parameters, can significantly
improve the performance of matching-dependent
circuits.
Three Op Amp Instrumentation Amplifier
APPLICATIO S I FOR ATIO
WU
UU
–
+
–
+
1/2 LT1112
OR
1/4 LT1114
A
1/2 LT1112
OR
1/4 LT1114
D
IN–
IN+
R1
10k
1%
R3
2.1k
1%
R8
200
R2
10k
1%
R4
100
0.5%
R5
100
0.5%
C1
33pF
R10
1M
R6
10k
0.5%
R7
9.88k
0.5%
R9
200
OUTPUT
–
+
LT1097 OR
1/4LT1114
B OR C
GAIN = 1000
TRIM R8 FOR GAIN
TRIM R9 FOR DC
COMMON MODE REJECTION
TRIM R10 FOR AC
COMMON MODE REJECTION
LT1112/14 AI02
Typical performance of the instrumentation amplifier:
Input offset voltage = 35
V
Offset voltage drift = 0.3
V/°C
Input bias current = 80pA
Input offset current = 100pA
Input resistance = 800G
Input noise = 0.42
VP-P
When the instrumentation amplifier is used with high
impedance sources, the LT1114 is recommended because
its CMRR vs frequency performance is better than the
LT1112’s. For example, with two matched 1M
source
resistors, CMRR at 100Hz is 100dB with the LT1114, 76dB
with the LT1112.
This difference is explained by the fact that capacitance
between adjacent pins on an IC package is about 0.25pF
(including package, socket and PC board trace capaci-
tances).
On the dual op amp package, positive input A is next to the
V – pin (AC ground), while positive input B has no AC
ground pin adjacent to it, resulting in a 0.25pF input
capacitance mismatch. At 100Hz, 0.25pF represents a
6.4 109 input impedance mismatch, which is only 76dB
higher than the 1M
source resistors.
On the quad package, all four inputs are adjacent to a
power supply terminal—therefore, there is no mismatch.
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