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| 型號： | LT1168CS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP INSTR PREC PROG 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 0.5 V/µs |
| 增益帶寬積： | 400kHz |
| 電流 - 輸入偏壓： | 80pA |
| 電壓 - 輸入偏移： | 20µV |
| 電流 - 電源： | 350µA |
| 電流 - 輸出 / 通道： | 32mA |
| 電壓 - 電源，單路/雙路(±)： | 4.6 V ~ 36 V，±2.3 V ~ 18 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1323 (CN2011-ZH PDF) |
12
LT1168
1168fa
voltage, G = (R1 + R2)/RG, to the unity-gain difference
amplifier A3. The common mode voltage is removed by
A3, resulting in a single-ended output voltage referenced
to the voltage on the REF pin. The resulting gain equation
is:
G = (49.4k
/RG) + 1
solving for the gain set resistor gives:
RG = 49.4k /(G – 1)
Table 1 shows appropriate 1% resistor values for a variety
of gains.
Table 1
DESIRED GAIN
RG
CLOSEST 1% VALUE
RESULTANT GAIN
1
Open
1
2
49400
49900
1.99
5
12350
12400
4.984
10
5488.89
5490
9.998
20
2600
2610
19.93
50
1008.16
1000
50.4
100
498.99
499
99.998
200
248.24
249
199.4
500
99
100
495
1000
49.95
49.4
1001
Input and Output Offset Voltage
The offset voltage of the LT1168 has two components: the
output offset and the input offset. The total offset voltage
referred to the input (RTI) is found by dividing the output
offset by the programmed gain (G) and adding it to the
input offset. At high gains the input offset voltage domi-
nates, whereas at low gains the output offset voltage
dominates. The total offset voltage is:
Total input offset voltage (RTI)
= input offset + (output offset/G)
Total output offset voltage (RTO)
= (input offset G) + output offset
Reference Terminal
The reference terminal is one end of one of the four 30k
resistors around the difference amplifier. The output
voltage of the LT1168 (Pin 6) is referenced to the voltage
on the reference terminal (Pin 5). Resistance in series
with the REF pin must be minimized for best common
mode rejection. For example, a 6
resistance from the
REF pin to ground will not only increase the gain error by
0.02% but will lower the CMRR to 80dB.
Input Voltage Range
The input voltage range for the LT1168 is specified in the
data sheet at 1.4V below the positive supply to 1.9V
above the negative supply for a gain of one. As the gain
increases the input voltage range decreases. This is due
to the IR drop across the internal gain resistors R1 and
R2 in Figure 1. For the unity gain condition there is no IR
drop across the gain resistors R1 and R2, the output of
the GM amplifiers is just the differential input voltage at
Pin 2 and Pin 3 (level shifted by one VBE from Q1 and Q2).
When a gain resistor is connected across Pins 1 and 8,
the output swing of the GM cells is now the differential
input voltage (level shifted by VBE) plus the differential
voltage times the gain (ratio of the internal gain resistors
to the external gain resistor across Pins 1 and 8). To
calculate how close to the positive rail the input (VIN) can
swing for a gain of 2 and a maximum expected output
swing of 10V, use the following equation:
+VS – VIN = – 0.5 – (VOUT/G) (G – 1)/2
Substituting yields:
– 0.5 – (10/2) (1/2) = – 3V
below the positive supply or 12V for a 15V supply. To
calculate how far above the negative supply the input can
swing for a gain of 10 with a maximum expected output
swing of –10V, the equation for the negative case is:
–VS + VIN = 1.5 – (VOUT/G) (G – 1)/2
Substituting yields:
1.5 – (–10/10) 9/2 = 6V
above the negative supply or – 9V for a negative supply
voltage of –15V. Figures 2 and 3 are for the positive
common mode and negative common mode cases
respectively.
THEORY OF OPERATIO
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