參數(shù)資料
型號: LT1187CS8
廠商: Linear Technology
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC AMP VIDEO DIFFRNC ADJ 8-SOIC
標(biāo)準(zhǔn)包裝: 100
應(yīng)用: 差分
電路數(shù): 1
-3db帶寬: 50MHz
轉(zhuǎn)換速率: 165 V/µs
電流 - 電源: 13mA
電流 - 輸出 / 通道: 20mA
電壓 - 電源,單路/雙路(±): 4.75 V ~ 16 V,±2.38 V ~ 8 V
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 1322 (CN2011-ZH PDF)
LT1187
8
1187fa
APPLICATIONS INFORMATION
The primary use of the LT1187 is in converting high speed
differential signals to a single-ended output. The LT1187
video difference amplier has two uncommitted high
input impedance (+) and (–) inputs. The amplier has
another set of inputs which can be used for reference and
feedback. Additionally, this set of inputs give gain adjust
and DC control to the difference amplier. The voltage
gain of the LT1187 is set like a conventional operational
amplier. Feedback is applied to Pin 8, and it is optimized
for gains of 2 or greater. The amplier can be operated
single-ended by connecting either the (+) or (–) inputs to
the +/REF (Pin 1). The voltage gain is set by the resistors:
(RFB + RG)/RG.
Like the single-ended case, the differential voltage gain is
set by the external resistors: (RFB + RG)/RG. The maximum
input differential signal for which the output will respond
is approximately ±0.38V.
Power Supply Bypassing
The LT1187 is quite tolerant of power supply bypassing.
In some applications a 0.1F ceramic disc capacitor placed
1/2 inch from the amplier is all that is required. In ap-
plications requiring good settling time, it is important to
use multiple bypass capacitors. A 0.1F ceramic disc in
parallel with a 4.7F tantalum is recommended.
Calculating the Output Offset Voltage
Both input stages contribute to the output offset voltage at
Pin 6. The feedback correction forces balance in the input
stages by introducing an input VOS at Pin 8. The complete
expression for the output offset voltage is:
VOUT = (VOS + IOS(RS) + IB(RREF)) (RFB+ RG)/RG + IB(RFB)
RS represents the input source resistance, typically 75Ω,
and RREF represents the nite source impedance from the
DC reference voltage, for VREF grounded, RREF = 0Ω. The
IOS is normally a small contributor and the expression
simplies to:
VOUT = VOS(RFB + RG)/RG + IB(RFB)
If RFB is limited to 1k the last term of the equation con-
tributes only 2mV, since IB is less than 2A.
V +
7
6
LT1187
V
4
1
8
OUT
V
+
3
2
IN
V
S/D
5
AV = +
RFB +
RFB
7
6
LT1187
4
1
8
OUT
V
+
3
2
IN DIFF
V
S/D
5
RFB
LT1187 AI01
7
6
LT1187
4
+/REF
1
–/FB
8
OUT
V
+
3
2
S/D
5
VO =
RFB +
RFB
7
6
LT1187
4
1
8
OUT
V
+
3
2
IN
V
S/D
5
AV = –
RFB +
RFB
IN
V
IN
V
(
( VIN DIFF
RFB
( ( VIN
+/REF
–/FB
+/REF
–/FB
+/REF
–/FB
RG
VO = (V
RFB +
IN DIFF + VIN)
RG
IN DIFF
V
RG
RG
V +
V
V +
V
V +
V
ILT1187 F01
+ 1 REF
RREF
RG
8
RFB
6
350
mA
+
3
RS
345
mA
2
RS
7V +
RE
1.1k
RE
1.1k
4V
Q1
Q2
Q3
Q4
Figure 1. Simplied Input Stage Schematic
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