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參數(shù)資料
| 型號(hào)： | LT1209CS#TRPBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP QUAD 45MHZ H-S 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 4 |
| 轉(zhuǎn)換速率： | 400 V/µs |
| 增益帶寬積： | 45MHz |
| 電流 - 輸入偏壓： | 4µA |
| 電壓 - 輸入偏移： | 1000µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 40mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 30 V，±2.5 V ~ 15 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SO |
| 包裝： | 帶卷 (TR) |
LT1208/LT1209
6
CC
HARA TERISTICS
UW
A
TYPICALPERFOR
CE
Gain-Bandwidth and Phase Margin
Total Harmonic Distortion
vs Supply Voltage
Slew Rate vs Supply Voltage
vs Frequency
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Layout and Passive Components
As with any high speed operational amplifier, care must be
taken in board layout in order to obtain maximum perfor-
mance. Key layout issues include: use of a ground plane,
minimization of stray capacitance at the input pins, short
lead lengths, RF-quality bypass capacitors located close
to the device (typically 0.01
F to 0.1F), and use of low
ESR bypass capacitors for high drive current applications
(typically 1
F to 10F tantalum). Sockets should be
avoided when maximum frequency performance is re-
quired, although low profile sockets can provide reason-
able performance up to 50MHz. For more details see
Design Note 50. The parallel combination of the feedback
resistor and gain setting resistor on the inverting input
combine with the input capacitance to form a pole which
can cause peaking. If feedback resistors greater than 5k
are used, a parallel capacitor of value
CF ≥ RG × CIN/RF
should be used to cancel the input pole and optimize
dynamic performance. For unity-gain applications where
a large feedback resistor is used, CF should be greater than
or equal to CIN.
Capacitive Loading
The LT1208/LT1209 amplifiers are stable with capacitive
loads. This is accomplished by sensing the load induced
output pole and adding compensation at the amplifier gain
node. As the capacitive load increases, both the bandwidth
and phase margin decrease so there will be peaking in the
frequency domain and in the transient response. The
photo of the small-signal response with 1000pF load
shows 50% peaking. The large-signal response with a
10,000pF load shows the output slew rate being limited by
the short-circuit current. To reduce peaking with capaci-
tive loads, insert a small decoupling resistor between the
output and the load, and add a capacitor between the
output and inverting input to provide an AC feedback path.
Coaxial cable can be driven directly, but for best pulse
fidelity the cable should be doubly terminated with a
resistor in series with the output.
SUPPLY VOLTAGE (±V)
0
GAIN-BANDWIDTH
(MHz)
20
1208/09 G19
5
10
15
60
55
50
45
40
35
30
25
20
62
60
58
56
54
52
50
48
46
PHASE
MARGIN
(DEG)
PHASE MARGIN
GAIN BANDWIDTH
TA = 25°C
SUPPLY VOLTAGE (±V)
0
SLEW
RATE
(V/
s)
20
1208/09 G20
5
10
15
600
500
400
300
200
100
–SR
+SR
TA = 25°C
AV = –1
FREQUENCY (Hz)
0.001
TOTAL
HARMONIC
DISTORTION
(%)
0.01
10
1k
10k
1208/09 G21
100
100k
AV = –1
AV = 1
TA = 25°C
VOUT = 3VRMS
RL = 500
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