TYPICAL PERFORMANCE CHARA" />
參數資料
型號: LT1222IS8#TRPBF
廠商: Linear Technology
文件頁數: 9/12頁
文件大?。?/td> 0K
描述: IC OP-AMP 500MHZ 200V/US 8-SOIC
標準包裝: 2,500
系列: C-Load™
放大器類型: 通用
電路數: 1
轉換速率: 200 V/µs
增益帶寬積: 500MHz
電流 - 輸入偏壓: 100nA
電壓 - 輸入偏移: 100µV
電流 - 電源: 8mA
電流 - 輸出 / 通道: 26mA
電壓 - 電源,單路/雙路(±): ±5 V ~ 15 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SO
包裝: 帶卷 (TR)
6
LT1222
1222fc
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
Large Signal, AV = 10
Small Signal, AV = 10
RF = 909Ω
RG = 100
Ω
LT1222 TPC19
LT1222 TPC20
Large Signal, AV = 10,
CL = 10,000pF
LT1222 TPC21
Small Signal, AV = – 10
LT1222 TPC22
LT1222 TPC23
LT1222 TPC24
Large Signal, AV = – 10
Small Signal, AV = – 10,
CL = 1,000pF
RF = 909
Ω
RG = 100Ω
RF = 1k
RG = 100Ω (75)
RF = 1k
RG = 100
Ω (75)
VS = ±15V
VIN = 20mV
f = 5MHz
VS = ±15V
VIN = 20mV
f = 5MHz
VS = ±15V
VIN = 2V
f = 2MHz
VS = ±15V
VIN = 2V
f = 2MHz
APPLICATIONS INFORMATION
WU
U
The LT1222 is stable in noise gains of 10 or greater and
may be inserted directly into HA2520/2/5, HA2541/2/4,
AD817, AD847, EL2020, EL2044 and LM6361 applica-
tions, provided that the nulling circuitry is removed and
the amplifier configuration has a high enough noise gain.
The suggested nulling circuit for the LT1222 is shown in
the following figure.
Layout and Passive Components
The LT1222 amplifier is easy to apply and tolerant of less
than ideal layouts. For maximum performance (for ex-
ample, fast settling time) use a ground plane, short lead
lengths and RF-quality bypass capacitors (0.01
μFto0.1μF).
For high drive current applications use low ESR bypass
capacitors (1
μF to 10μF tantalum). Sockets should be
avoided when maximum frequency performance is re-
quired. For more details see Design Note 50. Feedback
resistors greater than 5k are not recommended because a
pole is formed with the input capacitance which can cause
peaking or oscillations. Stray capacitance on Pin 5 should
be minimized. Bias current cancellation circuitry is em-
ployed on the inputs of the LT1222 so the input bias current
and input offset current have identical specifications. For
this reason, matching the impedance on the inputs to
reduce bias current errors is not necessary.
Offset Nulling
LT1222 AI01
V+
V
0.1
μF
0.1
μF
5k
3
2
4
7
6
8
1
LT1222
+
RF = 909Ω
RG = 100
Ω
VS =
±15V
VIN = 2V
f = 20kHz
RF = 1k
RG = 100Ω (75)
VS = ±15V
VIN = 15mV
f = 500kHz
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