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參數資料
| 型號： | LT1225CS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 6/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP-AMP HI-SPEED 150MHZ 8SOIC |
| 標準包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數： | 1 |
| 轉換速率： | 400 V/µs |
| 增益帶寬積： | 150MHz |
| 電流 - 輸入偏壓： | 4µA |
| 電壓 - 輸入偏移： | 500µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 40mA |
| 電壓 - 電源，單路/雙路(±)： | ±2.5 V ~ 15 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
LT1225
6
Small Signal, AV = 5
Small Signal, AV = – 5
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
The LT1225 may be inserted directly into HA2541, HA2544,
AD847, EL2020 and LM6361 applications, provided that
the amplifier configuration is a noise gain of 5 or greater,
and the nulling circuitry is removed. The suggested nulling
circuit for the LT1225 is shown below.
Offset Nulling
The large-signal response in both inverting and noninvert-
ing gain shows symmetrical slewing characteristics. Nor-
mally the noninverting response has a much faster rising
edge than falling edge due to the rapid change in input
common-mode voltage which affects the tail current of the
input differential pair. Slew enhancement circuitry has
been added to the LT1225 so that the noninverting slew
rate response is balanced.
Large Signal, AV = 5
Large Signal, AV = –5
Input Considerations
Resistors in series with the inputs are recommended for
the LT1225 in applications where the differential input
voltage exceeds
±6V continuously or on a transient basis.
An example would be in noninverting configurations with
high input slew rates or when driving heavy capacitive
loads. The use of balanced source resistance at each input
is recommended for applications where DC accuracy must
be maximized.
Capacitive Loading
The LT1225 is stable with all capacitive loads. This is
accomplished by sensing the load induced output pole and
adding compensation at the amplifier gain node. As the
capacitive load increases, both the bandwidth and phase
margin decrease so there will be peaking in the frequency
Layout and Passive Components
As with any high speed operational amplifier, care must be
taken in board layout in order to obtain maximum perfor-
mance. Key layout issues include: use of a ground plane,
minimization of stray capacitance at the input pins, short
lead lengths, RF-quality bypass capacitors located close
to the device (typically 0.01
F to 0.1F), and use of low
ESR bypass capacitors for high drive current applications
(typically 1
F to 10F tantalum). Sockets should be
avoided when maximum frequency performance is
required, although low profile sockets can provide
reasonable performance up to 50MHz. For more details
see Design Note 50. Feedback resistor values greater than
5k are not recommended because a pole is formed with the
input capacitance which can cause peaking. If feedback
resistors greater than 5k are used, a parallel
capacitor of 5pF to 10pF should be used to cancel the input
pole and optimize dynamic performance.
Transient Response
The LT1225 gain-bandwidth is 150MHz when measured at
1MHz. The actual frequency response in gain of 5 is
considerably higher than 30MHz due to peaking caused by
a second pole beyond the gain of 5 crossover point. This
is reflected in the small-signal transient response. Higher
noise gain configurations exhibit less overshoot as seen in
the inverting gain of 5 response.
–
+
3
2
1
8
5k
0.1
F
7
6
4
0.1
F
V+
V –
LT1225
LT1225 AI01
LT1225 AI02
LT1225 AI03
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