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參數(shù)資料
| 型號： | LT1317B |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 8-Bit Identity/Magnitude Comparators (P=Q) with Enable 20-PDIP 0 to 70 |
| 中文描述： | 微功耗，600kHz的PWM型DC / DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 447K |
| 代理商： | LT1317B |
7
LT1317/LT1317B
BLOCK DIAGRA
M
W
–
+
–
+
–
+
–
+
–
+
+
+
Σ
RAMP
GENERATOR
1.24V
REFERENCE
R
BIAS
V
C
1
g
m
FB
ENABLE
200mV
A = 2
FF
A1
COMPARATOR
A2
COMPARATOR
ERROR
AMPLIFIER
A4
0.08
DRIVER
SW
5
GND
1317 BD
Q3
Q
S
600kHz
OSCILLATOR
LBO
8
LBI
7
SHDN
3
SHUTDOWN
4
R1
(EXTERNAL)
V
OUT
R2
(EXTERNAL)
FB
2
APPLICATIO
S I
N
FOR
ATIO
U
OPERATION
The LT1317 combines a current mode, fixed frequency
PWM architecture with Burst Mode micropower operation
to maintain high efficiency at light loads. Operation can
best be understood by referring to the Block Diagram.
The error amplifier compares voltage at the FB pin with the
internal 1.24V bandgap reference and generates an error
signal V
C
. When V
C
decreases below the bias voltage on
hysteretic comparator A1, A1’s output goes low, turning
off all circuitry except the 1.24V reference, error amplifier
and low-battery detector. Total current consumption in
this state is 100
μ
A. As output loading causes the FB
voltage to decrease, V
C
increases causing A1’s output to
go high, in turn enabling the rest of the IC. Switch current
is limited to approximately 250mA initially after A1’s
output goes high. If the load is light, the output voltage
(and FB voltage) will increase until A1’s output goes low,
turning off the rest of the LT1317. Low frequency ripple
voltage appears at the output. The ripple frequency is
dependent on load current and output capacitance. This
Burst Mode operation keeps the output regulated and
reduces average current into the IC, resulting in high
efficiency even at load currents of 300
μ
A or less.
W
U
If the output load increases sufficiently, A1’s output remains
high, resulting in continuous operation. When the LT1317
is running continuously, peak switch current is controlled
by V
C
to regulate the output voltage. The switch is turned
on at the beginning of each switch cycle. When the sum-
mation of a signal representing switch current and a ramp
generator (introduced to avoid subharmonic oscillations at
duty factors greater than 50%) exceeds the V
C
signal,
comparator A2 changes state, resetting the flip-flop and
turning off the switch. Output voltage increases as switch
current is increased. The output, attenuated by a resistor
divider, appears at the FB pin, closing the overall loop.
Frequency compensation is provided by an external series
RC network and an optional capacitor connected between
the V
C
pin and ground.
Low-battery detector A4’s open collector output (LBO) pulls
low when the LBI pin voltage drops below 200mV. There
is no hysteresis in A4, allowing it to be used as an amplifier
in some applications. The low-battery detector remains
active in shutdown. To enable the converter, SHDN must
be left floating or tied to a voltage between 1.4V and 6V.
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