參數(shù)資料
型號： LT1336CS
廠商： LINEAR TECHNOLOGY CORP
元件分類： MOSFETs
英文描述： Half-Bridge N-Channel Power MOSFET Driver with Boost Regulator
中文描述： 1.5 A HALF BRDG BASED MOSFET DRIVER, PDSO16
封裝： 0.150 INCH, PLASTIC, SO-16
文件頁數(shù)： 3/16頁
文件大?。?/td> 365K
代理商： LT1336CS
3
LT1336
V
IS
V
ISHYS
V
SAT
I
SENSE
Peak Current Threshold
I
SENSE
Hysteresis
Switch Saturation Voltage
V
TSOURCE
= 60V, V
BOOST
= 68V, V
+
– V
ISENSE
V
TSOURCE
= 60V, V
BOOST
= 68V
V
ISENSE
= V
+
, V
BOOST
– V
TSOURCE
= 9V,
I
SW
= 100mA
V
TSOURCE
= 40V, V
INTOP
= V
INBOTTOM
= 0.8V,
I
BOOST
= 10mA, V
BOOST
– V
TSOURCE
V
INTOP
(+) Transition, V
INBOTTOM
= 0.8V,
Measured at V
TGATE DR
– V
TSOURCE
(Note 4)
V
INBOTTOM
(+) Transition, V
INTOP
= 0.8V,
Measured at V
BGATE DR
(Note 4)
V
INTOP
(–) Transition, V
INBOTTOM
= 0.8V,
Measured at V
TGATE DR
– V
TSOURCE
(Note 4)
V
INBOTTOM
(–) Transition, V
INTOP
= 0.8V,
Measured at V
BGATE DR
(Note 4)
V
INTOP
(+) Transition, V
INBOTTOM
= 0.8V,
Measured at V
TGATE DR
– V
TSOURCE
(Note 4)
V
INBOTTOM
(+) Transition, V
INTOP
= 0.8V,
Measured at V
BGATE DR
(Note 4)
V
INTOP
(–) Transition, V
INBOTTOM
= 0.8V,
Measured at V
TGATE DR
– V
TSOURCE
(Note 4)
V
INBOTTOM
(–) Transition, V
INTOP
= 0.8V,
Measured at V
BGATE DR
(Note 4)
V
INBOTTOM
(+) Transition, V
INTOP
= 2V,
Measured at V
TGATE DR
– V
TSOURCE
(Note 4)
V
INTOP
(+) Transition, V
INBOTTOM
= 2V,
Measured at V
BGATE DR
(Note 4)
V
INBOTTOM
(–) Transition, V
INTOP
= 2V,
Measured at V
TGATE DR
– V
TSOURCE
(Note 4)
V
INTOP
(–) Transition, V
INBOTTOM
= 2V,
Measured at V
BGATE DR
(Note 4)
310
25
480
55
0.85
650
85
1.2
mV
mV
G
V
V
BOUT
V
BOOST
Regulated Output
10
10.6
11.2
V
t
r
Top Gate Rise Time
G
130
200
ns
Bottom Gate Rise Time
G
90
200
ns
t
f
Top Gate Fall Time
G
60
140
ns
Bottom Gate Fall Time
G
60
140
ns
t
D1
Top Gate Turn-On Delay
G
250
500
ns
Bottom Gate Turn-On Delay
G
200
400
ns
t
D2
Top Gate Turn-Off Delay
G
300
600
ns
Bottom Gate Turn-Off Delay
G
200
400
ns
t
D3
Top Gate Lockout Delay
G
300
600
ns
Bottom Gate Lockout Delay
G
250
500
ns
t
D4
Top Gate Release Delay
G
250
500
ns
Bottom Gate Release Delay
G
200
400
ns
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ELECTRICAL CHARACTERISTICS
Test Circuit, T
A
= 25
°
C, V
+
= V
BOOST
= 12V, V
TSOURCE
= 0V, and Pins 1, 16
open. Gate Feedback pins connected to Gate Drive pins unless otherwise specified.
The
G
denotes specifications which apply over the full operating
temperature range.
Note 1:
T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LT1336CN/LT1336IN: T
J
= T
A
+ (P
D
)(70
°
C/W)
LT1336CS/LT1336IS: T
J
= T
A
+ (P
D
)(110
°
C/W)
Note 2:
Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Typical Performance
Characteristics and Applications Information sections.
Note 3:
Pins 1 and 16 connected to each end of the inductor. Booster is
free running.
Note 4:
See Timing Diagram. Gate rise times are measured from 2V to 10V
and fall times are measured from 10V to 2V. Delay times are measured
from the input transition to when the gate voltage has risen to 2V or
decreased to 10V.
相關(guān)PDF資料
PDF描述
LT1336IN Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs 20-PDIP 0 to 70
LT1336IS Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs 20-SO 0 to 70
LT1339C Octal Buffers/Drivers With 3-State Outputs 20-SOIC 0 to 70
LT1339 High Efficiency, Synchronous, 4-Switch Buck-Boost Controller
LT1339CN Octal Buffers/Drivers With 3-State Outputs 20-SOIC 0 to 70
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