TYPICAL PERFORMAN" />
參數(shù)資料
型號: LT1352IS8#TR
廠商: Linear Technology
文件頁數(shù): 16/16頁
文件大?。?/td> 0K
描述: IC OP AMP HI SPD 3MHZ DUAL 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: C-Load™
放大器類型: 電壓反饋
電路數(shù): 2
轉(zhuǎn)換速率: 200 V/µs
增益帶寬積: 3MHz
電流 - 輸入偏壓: 20nA
電壓 - 輸入偏移: 200µV
電流 - 電源: 250µA
電流 - 輸出 / 通道: 13.4mA
電壓 - 電源,單路/雙路(±): ±2.5 V ~ 15 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 帶卷 (TR)
9
LT1352/LT1353
13523fa
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
Small-Signal Transient
(AV = 1)
Small-Signal Transient
(AV = – 1)
Small-Signal Transient
(AV = – 1, CL = 1000pF)
1352/53 G33
1352/53 G32
1352/53 G31
Large-Signal Transient
(AV = 1)
Large-Signal Transient
(AV = – 1)
Large-Signal Transient
(AV = 1, CL = 10,000pF)
1352/53 G36
1352/53 G35
1352/53 G34
APPLICATIONS INFORMATION
WU
U
Layout and Passive Components
The LT1352/LT1353 amplifiers are easy to use and toler-
ant of less than ideal layouts. For maximum performance
(for example, fast 0.01% settling) use a ground plane,
short lead lengths and RF-quality bypass capacitors (0.01
F
to 0.1
F). For high drive current applications use low ESR
bypass capacitors (1
F to 10F tantalum).
The parallel combination of the feedback resistor and
gain setting resistor on the inverting input can combine
with the input capacitance to form a pole which can cause
peaking or even oscillations. If feedback resistors greater
than 10k are used, a parallel capacitor of value, CF >
(RG)(CIN/RF), should be used to cancel the input pole and
optimize dynamic performance. For applications where
the DC noise gain is one and a large feedback resistor is
used, CF should be greater than or equal to CIN. An
example would be an I-to-V converter as shown in the
Typical Applications section.
Capacitive Loading
The LT1352/LT1353 are stable with any capacitive load.
As the capacitive load increases, both the bandwidth and
phase margin decrease so there will be peaking in the
frequency domain and in the transient response. Graphs
of Frequency Response vs Capacitive Load, Capacitive
Load Handling and the transient response photos clearly
show these effects.
Input Considerations
Each of the LT1352/LT1353 inputs is the base of an NPN
and a PNP transistor whose base currents are of opposite
polarity and provide first-order bias current cancellation.
Because of variation in the matching of NPN and PNP beta,
the polarity of the input bias current can be positive or
negative. The offset current does not depend on NPN/PNP
beta matching and is well controlled. The use of balanced
source resistance at each input is recommended for
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