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| 型號(hào)： | LT1362CN#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OP-AMP HI-SPD 50MHZ QUAD14DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | C-Load™ |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 4 |
| 轉(zhuǎn)換速率： | 800 V/µs |
| 增益帶寬積： | 50MHz |
| 電流 - 輸入偏壓： | 300nA |
| 電壓 - 輸入偏移： | 300µV |
| 電流 - 電源： | 4mA |
| 電流 - 輸出 / 通道： | 34mA |
| 電壓 - 電源，單路/雙路(±)： | ±2.5 V ~ 15 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1318 (CN2011-ZH PDF) |
10
LT1361/LT1362
tion with large, sustained differential inputs. Under
normal, closed-loop operation, an increase of power dis-
sipation is only noticeable in applications with large slewing
outputs and is proportional to the magnitude of the
differential input voltage and the percent of the time that
the inputs are apart. Measure the average supply current
for the application in order to calculate the power dissipa-
tion.
Capacitive Loading
The LT1361/LT1362 are stable with any capacitive load.
This is accomplished by sensing the load induced output
pole and adding compensation at the amplifier gain node.
As the capacitive load increases, both the bandwidth and
phase margin decrease so there will be peaking in the
frequency domain and in the transient response as shown
in the typical performance curves. The photo of the small
signal response with 500pF load shows 60% peaking. The
large signal response shows the output slew rate being
limited to 5V/
s by the short-circuit current. Coaxial cable
can be driven directly, but for best pulse fidelity a resistor
of value equal to the characteristic impedance of the cable
(i.e., 75
) should be placed in series with the output. The
other end of the cable should be terminated with the same
value resistor to ground.
Circuit Operation
The LT1361/LT1362 circuit topology is a true voltage
feedback amplifier that has the slewing behavior of a
current feedback amplifier. The operation of the circuit can
be understood by referring to the simplified schematic.
The inputs are buffered by complementary NPN and PNP
emitter followers which drive a 500
resistor. The input
voltage appears across the resistor generating currents
which are mirrored into the high impedance node. Comple-
mentary followers form an output stage which buffers the
gain node from the load. The bandwidth is set by the input
resistor and the capacitance on the high impedance node.
The slew rate is determined by the current available to
charge the gain node capacitance. This current is the
differential input voltage divided by R1, so the slew rate is
proportional to the input. Highest slew rates are therefore
seen in the lowest gain configurations. For example, a 10V
output step in a gain of 10 has only a 1V input step,
APPLICATIONS INFORMATION
WU
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whereas the same output step in unity gain has a 10 times
greater input step. The curve of Slew Rate vs Input Level
illustrates this relationship. The LT1361/LT1362 are tested
for slew rate in a gain of –2 so higher slew rates can be
expected in gains of 1 and –1, and lower slew rates in
higher gain configurations.
The RC network across the output stage is bootstrapped
when the amplifier is driving a light or moderate load and
has no effect under normal operation. When driving a
capacitive load (or a low value resistive load) the network
is incompletely bootstrapped and adds to the compensa-
tion at the high impedance node. The added capacitance
slows down the amplifier which improves the phase
margin by moving the unity-gain frequency away from the
pole formed by the output impedance and the capacitive
load. The zero created by the RC combination adds phase
to ensure that even for very large load capacitances, the
total phase lag can never exceed 180 degrees (zero phase
margin) and the amplifier remains stable.
Power Dissipation
The LT1361/LT1362 combine high speed and large output
drive in small packages. Because of the wide supply
voltage range, it is possible to exceed the maximum
junction temperature under certain conditions. Maximum
junction temperature (TJ) is calculated from the ambient
temperature (TA) and power dissipation (PD) as follows:
LT1361CN8: TJ = TA + (PD x 130°C/W)
LT1361CS8: TJ = TA + (PD x 190°C/W)
LT1362CN: TJ = TA + (PD x 110°C/W)
LT1362CS: TJ = TA + (PD x 150°C/W)
Worst case power dissipation occurs at the maximum
supply current and when the output voltage is at 1/2 of
either supply voltage (or the maximum swing if less than
1/2 supply voltage). For each amplifier PDMAX is:
PDMAX = (V+ – V–)(ISMAX) + (V+/2)2/RL
Example: LT1362 in S16 at 70
°C, VS = ±5V, RL = 100
PDMAX = (10V)(5.6mA) + (2.5V)2/100 = 119mW
TJMAX = 70°C + (4 x 119mW)(150°C/W) = 141°C
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| LT1362CS | 功能描述:IC OP-AMP HISPD 50MHZ QUAD16SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:C-Load™ 標(biāo)準(zhǔn)包裝:150 系列:- 放大器類型:音頻 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:5 V/µs 增益帶寬積:12MHz -3db帶寬:- 電流 - 輸入偏壓:100nA 電壓 - 輸入偏移:500µV 電流 - 電源:6mA 電流 - 輸出 / 通道:50mA 電壓 - 電源，單路/雙路(±):4 V ~ 32 V，±2 V ~ 16 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| LT1362CS#PBF | 功能描述:IC OP-AMP HISPD 50MHZ QUAD16SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:C-Load™ 標(biāo)準(zhǔn)包裝:2,500 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:- 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
| LT1362CS#TR | 功能描述:IC OPAMP QUAD 50MHZ HS LP 16SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:C-Load™ 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
| LT1362CS#TRPBF | 功能描述:IC OP-AMP HISPD 50MHZ QUAD16SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:C-Load™ 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
| LT1362CSPBF | 制造商:Linear Technology 功能描述:Op Amplifier Quad 50MHz 800V/us SOIC16 |
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