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參數(shù)資料
| 型號： | LT1374C |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Binary Counters With 3-State Outputs 20-PDIP 0 to 70 |
| 中文描述： | 4.5A，500kHz降壓型開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 261K |
| 代理商： | LT1374C |
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20
LT1374
APPLICATIO
S I
FOR
ATIO
U
frequency. By contrast, the LT1374 uses a “current mode”
architecture to help alleviate phase shift created by the
inductor. The basic connections are shown in Figure 9.
Figure 10 shows a Bode plot of the phase and gain of the
power section of the LT1374, measured from the V
C
pin to
the output. Gain is set by the 5.3A/V transconductance of
the LT1374 power section and the effective complex
impedance from output to ground. Gain rolls off smoothly
above the 600Hz pole frequency set by the 100
μ
F output
capacitor. Phase drop is limited to about 70
°
. Phase
recovers and gain levels off at the zero frequency (
≈
16kHz)
set by capacitor ESR (0.1
).
Error amplifier transconductance phase and gain are shown
in Figure 11. The error amplifier can be modeled as a
transconductance of 2000
μ
Mho, with an output imped-
ance of 200k
in parallel with 12pF. In all practical
W
U
U
applications, the compensation network from V
C
pin to
ground has a much lower impedance than the output
impedance of the amplifier at frequencies above 500Hz.
This means that the error amplifier characteristics them-
selves do not contribute excess phase shift to the loop, and
the phase/gain characteristics of the error amplifier sec-
tion are completely controlled by the external compensa-
tion network.
In Figure 12, full loop phase/gain characteristics are
shown with a compensation capacitor of 1.5nF, giving the
error amplifier a pole at 530Hz, with phase rolling off to 90
°
and staying there. The overall loop has a gain of 74dB at
low frequency, rolling off to unity-gain at 100kHz. Phase
shows a two-pole characteristic until the ESR of the output
capacitor brings it back above 10kHz. Phase margin is
about 75
°
at unity-gain.
Figure 9. Model for Loop Response
Figure 10. Response from V
C
Pin to Output
FREQUENCY (Hz)
G
C
P
C
40
20
0
–20
–40
40
0
–40
–80
–120
10
1k
10k
1M
1374 F10
100
100k
GAIN
PHASE
V
IN
= 10V
V
OUT
= 5V
I
OUT
= 2A
Figure 11. Error Amplifier Gain and Phase
FREQUENCY (Hz)
G
μ
M
P
3000
2500
2000
1500
1000
500
200
150
100
50
0
–50
100
10k
100k
10M
1374 F11
1k
1M
GAIN
PHASE
R
200k
C
12pF
V
C
ERROR AMPLIFIER EQUIVALENT CIRCUIT
R
LOAD
= 50
V
FB
2
×
10
–3
)
(
FREQUENCY (Hz)
L
L
80
60
40
20
0
–20
200
150
100
50
0
–50
10
1k
10k
1M
1374 F12
100
100k
GAIN
PHASE
V
IN
= 10V
V
OUT
= 5V, I
OUT
= 2A
C
OUT
= 100
μ
C
C
= 1.5nF, R
C
= 0, L = 10
μ
H
Figure 12. Overall Loop Characteristics
–
+
2.42V
V
SW
V
C
LT1374
GND
1374 F09
R1
OUTPUT
ESR
C
F
C
C
R
C
ERROR
AMPLIFIER
FB
R2
C1
CURRENT MODE
POWER STAGE
g
m
= 5.3A/V
+
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