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參數(shù)資料
| 型號： | LT1374CT7 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Synchronous 4-Bit Up/Down Binary Counters With 3-State Outputs 20-SO 0 to 70 |
| 中文描述： | 8.5 A SWITCHING REGULATOR, 560 kHz SWITCHING FREQ-MAX, PSFM7 |
| 封裝： | PLASTIC, TO-220, 7 PIN |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 261K |
| 代理商： | LT1374CT7 |
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19
LT1374
APPLICATIO
S I
FOR
ATIO
U
W
U
U
different cause of subharmonic switching before assum-
ing that the cause is insufficient slope compensation.
Application Note 19 has more details on the theory of slope
compensation.
At power-up, when V
C
is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows the
frequency foldback to operate in the shorted output con-
dition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
1.5V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
THERMAL CALCULATIONS
Power dissipation in the LT1374 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
P
R
V
V
ns I
V
f
SW
SW OUT
OUT
IN
OUT
IN
=
) (
)
+
(
)( )( )
2
24
Boost current loss:
P
V
I
V
BOOST
OUT
OUT
IN
=
(
)
2
50
/
Quiescent current loss:
P
V
V
V
V
Q
IN
OUT
OUT
IN
=
(
)
+
(
)
+
(
)
0 001
0 005
0 002
2
R
SW
= Switch resistance (
≈
0.07)
24ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with V
IN
= 10V, V
OUT
= 5V and I
OUT
= 3A:
P
W
P
W
P
W
SW
BOOST
Q
=
(
)( ) ( )
+
10
0 36
2
/
( )( )
=
+
=
=
( ) (
)
=
=
)
+
)
+
( ) (
)
=
0 07 3
.
5
24 10
3 10 500 10
0 32
.
068
.
5
3 50
10
0 15
.
10 0 001
5 0 005
.
5
0 002
.
10
0 04
.
2
9
3
2
.
.
Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W.
Thermal resistance for LT1374 package is influenced by
the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 80
°
C/W. No plane will increase resistance to about
120
°
C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
T
J
= T
A
+
θ
JA
(P
TOT
)
With the SO-8 package (
θ
JA
= 80
°
C/W), at an ambient
temperature of 50
°
C,
T
J
= 50 + 80 (0.87) = 120
°
C
For the DD package with a good copper plane under the
device, thermal resistance will be about 30
°
C/W. For the
conditions above:
T
J
= 50 + 30 (0.87) = 76
°
C
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
FREQUENCY COMPENSATION
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also intro-
duce multiple poles into the feedback loop. The inductor
and output capacitor on a conventional step-down con-
verter actually form a resonant tank circuit that can exhibit
peaking and a rapid 180
°
phase shift at the resonant
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