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參數(shù)資料
| 型號(hào)： | LT1374HV |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Binary Counters With 3-State Outputs 20-SO 0 to 70 |
| 中文描述： | 4.5A，500kHz降壓型開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 261K |
| 代理商： | LT1374HV |
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7
LT1374
BLOCK DIAGRA
M
W
The LT1374 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscilla-
tor pulse which sets the R
S
flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180
°
shift will occur.
The current fed system will have 90
°
phase shift at a much
lower frequency, but will not have the additional 90
°
shift
until well beyond the LC resonant frequency. This makes
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.
Most of the circuitry of the LT1374 operates from an
internal 2.9V bias line. The bias regulator normally draws
power from the regulator input pin, but if the BIAS pin is
connected to an external voltage higher than 3V, bias
power will be drawn from the external source (typically the
regulated output voltage). This will improve efficiency if
the BIAS pin voltage is lower than regulator input voltage.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing the switch to saturate. This
boosted voltage is generated with an external capacitor
and diode. Two comparators are connected to the shut-
down pin. One has a 2.38V threshold for undervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.
Figure 1. Block Diagram
–
+
–
+
–
+
–
+
Σ
INPUT
2.9V BIAS
REGULATOR
500kHz
OSCILLATOR
FREQUENCY
SHIFT CIRCUIT
V
SW
FB
V
C
LOCKOUT
COMPARATOR
GND
1374 BD
SLOPE COMP
0.01
BIAS*
INTERNAL
V
CC
CURRENT
SENSE
AMPLIFIER
VOLTAGE GAIN = 20
SYNC
SHDN
SHUTDOWN
COMPARATOR
CURRENT
COMPARATOR
ERROR
AMPLIFIER
g
m
= 2000
μ
Mho
FOLDBACK
CURRENT
LIMIT
CLAMP
BOOST
R
FLIP-FLOP
DRIVER
CIRCUITRY
S
R
0.9V
Q2
Q1
POWER
SWITCH
2.42V
2.38V
*BIAS PIN IS AVAILABLE ONLY ON THE S0-8 PACKAGE
–
+
0.4V
3.5
μ
A
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