參數(shù)資料
型號: LT1374IR-5
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS
中文描述: 8.5 A SWITCHING REGULATOR, 560 kHz SWITCHING FREQ-MAX, PSSO7
封裝: PLASTIC, D2PAK-7
文件頁數(shù): 15/28頁
文件大?。?/td> 261K
代理商: LT1374IR-5
15
LT1374
prevents the regulator from operating at source voltages
where these problems might occur.
Threshold voltage for lockout is about 2.38V, slightly less
than the internal 2.42V reference voltage. A 3.5
μ
A bias
current flows outof the pin at threshold. This internally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shut-
down current is not an issue, the error due to this current
can be minimized by making R
LO
10k or less. If shutdown
current is an issue, R
LO
can be raised to 100k, but the error
due to initial bias current and changes with temperature
should be considered.
R
k
R
R
V
V
V R
A
LO
HI
LO
IN
LO
=
(
)
=
(
)
(
)
10
2 38
2 38
3 5
to 100k 25k suggested
V
IN
= Minimum input voltage
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capaci-
tance to the switching nodes are minimized. If high resis-
tor values are used, the shutdown pin should be bypassed
with a 1000pF capacitor to prevent coupling problems
from the switch node. If hysteresis is desired in the
undervoltage lockout point, a resistor R
FB
can be added to
the output node. Resistor values can be calculated from:
[
(
=
( )(
R
R
V
V V
V
R
)
A
R
R
V
V
HI
LO
IN
OUT
FB
HI
OUT
=
+
)
(
)
+
]
2 38
1
2 38
/
2 3 5
.
μ
25k suggested for R
LO
V
IN
=
Input voltage at which switching stops as input
voltage descends to trip level
V = Hysteresis in input voltage level
APPLICATIO
S I
N
FOR
ATIO
U
W
U
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless
input rises back to 13.5V.
V is therefore 1.5V and
V
IN
= 12V. Let R
LO
= 25k.
[
(
(
(
R
k
k
A
k
k
R
k
k
HI
FB
=
+
(
)
+
)
]
=
)
=
)
=
=
25 12 2 38 1 5 5 1
.
1 5
2 38 25 3 5
.
25 10 41
.
2 29
114
114 5 1 5
380
. /
.
.
/ .
μ
SWITCH NODE CONSIDERATIONS
For maximum efficiency, switch rise and fall times are
made as short as possible. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the switch node is essential. B field
(magnetic) radiation is minimized by keeping catch diode,
switch pin, and input bypass capacitor leads as short as
possible. E field radiation is kept low by minimizing the
length and area of all traces connected to the switch pin
and BOOST pin. A ground plane should always be used
under the switcher circuitry to prevent interplane cou-
pling. A suggested layout for the critical components is
shown in Figure 5. Note that the feedback resistors and
compensation components are kept as far as possible
from the switch node. Also note that the high current
ground path of the catch diode and input capacitor are kept
very short and separate from the analog ground line.
The high speed switching current path is shown schemati-
cally in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, catch diode, and input capacitor is
the only one containing nanosecond rise and fall times. If
you follow this path on the PC layout, you will see that it is
irreducibly short. If you move the diode or input capacitor
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