參數(shù)資料
型號(hào): LT1424IS8-9
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 穩(wěn)壓器
英文描述: Isolated Flyback Switching Regulator with 9V Output
中文描述: 1.9 A SWITCHING REGULATOR, 320 kHz SWITCHING FREQ-MAX, PDSO8
封裝: 0.150 INCH, PLASTIC, SO-8
文件頁(yè)數(shù): 12/16頁(yè)
文件大?。?/td> 141K
代理商: LT1424IS8-9
12
LT1424-5
APPLICATIO
S I
FOR
ATIO
U
pulse extends beyond the flyback pulse, loss of regulation
will occur. The onset of this condition can be determined
by setting the width of the flyback pulse equal to the sum
of the flyback enable delay, t
ED
, plus the minimum enable
time, t
EN
. Minimum power delivered to the load is then:
2
)
= (V
OUT
)(I
OUT
)
W
U
U
somewhat duty cycle dependent due to internal slope
compensation action.
Short-circuit conditions are handled by the same mecha-
nism. The output switch turns on, peak current is quickly
reached and the switch is turned off. Because the output
switch is only on for a small fraction of the available period,
internal power dissipation is controlled. (The LT1424-5
contains an internal overtemperature shutdown circuit,
that disables switch action, just in case.)
THERMAL CONSIDERATIONS
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. The packages are rated at 110
°
C/W
for SO-8 and 130
°
C/W for N8.
Average supply current (including driver current) is:
35
)
I
SW
= Switch current
DC = On switch duty cycle
Switch power dissipation is given by:
P
SW
= (I
SW
)
2
(R
SW
)(DC)
R
SW
= Output switch ON resistance
Total power dissipation of the die is the sum of supply
current times supply voltage plus switch power:
P
D(TOTAL)
= (I
IN
V
IN
) + P
SW
I
SW
)
I
IN
= 7mA + DC
where,
FREQUENCY COMPENSATION
Loop frequency compensation is performed by connect-
ing a capacitor from the output of the error amplifier (V
C
pin) to ground. An additional series resistor, often
required in traditional current mode switcher controllers is
usually not required; and can even prove detrimental. The
phase margin improvement traditionally offered by this
extra resistor will usually be already accomplished by the
nonzero secondary circuit impedance, which adds a “zero”
to the loop response.
1
f
L
SEC
)
)
Min Power =
[V
OUT
(t
EN
+ t
ED
)]
2
Which yields a minimum output constraint:
2
)
f = Switching frequency (nominally 285kHz)
L
SEC
= Transformer secondary side inductance
V
OUT
= Output voltage
t
ED
= Enable delay time
t
EN
= Minimum enable time
1
f(V
OUT
)
L
SEC
)
)
I
OUT(MIN)
=
(t
ED
+ t
EN
)
2
, where
In reality, the previously derived expression is a conserva-
tive one, as it assumes perfectly “square” waveforms,
which is not the case at light load. Furthermore, the
equation was set up to yield just the onset of control error.
In other words, while the equation suggests a minimum
load current of perhaps 3mA, laboratory observations
suggest operation down to 1mA to 2mA before significant
output voltage rise is observed. Nevertheless, this situa-
tion is addressed in the application by the use of a fixed
1.8k load resistor, which preloads the supply with a
nominal 2.8mA.
MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
The LT1424-5 is a current mode controller. It uses the V
C
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V
C
node, nominally 1.9V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit, which is
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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