參數(shù)資料
型號(hào): LT1432CN8
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 穩(wěn)壓器
英文描述: 5V High Efficiency Step-Down Switching Regulator Controller
中文描述: SWITCHING CONTROLLER, PDIP8
封裝: PLASTIC, DIP-8
文件頁(yè)數(shù): 15/28頁(yè)
文件大?。?/td> 611K
代理商: LT1432CN8
15
LT1432
Current limit at V
OUT
= 5V
Current limit (output shorted)
Minimum Input Voltage
Minimum input voltage for a buck converter using the
LT1432 is actually limited by the IC switcher used with it.
There are three factors which contribute to the minimum
voltage. At very light loads, the charge pump technique
used to provide the floating power for the switcher chip is
unable to provide sufficient current. See Figure 16 for the
minimum load required as a function of input voltage
when operating in the normal mode.
At moderate to heavy loads, switch on-resistance and
maximum duty cycle will limit minimum input voltage.
Graphs in the Typical Performance Characteristics section
show minimum input voltage as a function of load current.
At moderate loads, maximum switch duty cycle is the
limiting factor. The LT1070 family, operating at 40kHz has
a maximum duty cycle of about 94%. The LT1170 family
runs at 100kHz and has a maximum duty cycle of 90%. The
LT1270 and LT1271 operate at 60kHz with a maximum
duty cycle of 92%. The curves were generated using the
expected worst case duty cycle for these devices over the
commercial operating temperature range (0
°
C to 100
°
C
junction temperature). Note that the lower frequency
devices will operate at lower input voltage because of their
higher duty cycle. These devices will require larger induc-
tors, however. (Yet another example of the universal “no
free lunch” syndrome).
U
S
A
O
PPLICATI
IU
U
voltage. This extra sense voltage is set by output voltage
and R4 under normal loads, but drops to near zero when
the output is shorted.
The 40
μ
A bias current flowing out of the V
LIM
pin must be
accounted for when calculating a value for R4. This current
flows through R3, causing a 4mV decreasein sense
voltage for R3 = 100
. The following formulas define
current limit conditions:
Current limit at V
OUT
= 5V
V
S
= Desired full load sense voltage.
I
MAX
= Peak load current (for any time greater than
50
μ
s)
I
B
= V
LIM
pin bias current (
40mA)
To maintain high efficiency and avoid any startup prob-
lems with loads that have non-linear V/I characteristics, a
100mV (average) sense voltage is suggested for foldback
current limiting. The suggested value for R3 is 100
. This
is a compromise value to keep errors due to V
LIM
bias
current low, and to minimize current drain on the output
created by the R3/R4 path. From the previous design
example, with I
MAX
= 2A and I
RIP
/2 = 0.55A, and assuming
R3 = 100
, V
LIM
= 100mV:
=
60mV –I R3 + V
R3
R4
R
I
2
R
Short Circuit Current = 60mV –I (R3)
R
R
=
V
I
(1.2)
R4 =
V
R3
( )
V – 60mV+I R3 + R
I
2
OUT
SENSE
RIP
SENSE
SENSE
SENSE
LIM
MAX
OUT
SENSE
RIP
)
(
)
)
=
(
)
=
60mV –100
40 A
0.042
1.33A
R
= 100mV
2A 1.2
0.042
SENSE
)
=
R4 =
5V 100
100mV – 60mV+100
40 A – 0.042 0.55
7.45k
)
(
)
=
=
)
+
(
)
=
60mV – 40 A 100
5V
100
7.45k
0.042 0.55
0.042
2.38A
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