參數(shù)資料
型號(hào): LT1468IS8
廠商: LINEAR TECHNOLOGY CORP
元件分類: 運(yùn)動(dòng)控制電子
英文描述: 90MHz, 22V/us 16-Bit Accurate Operational Amplifier
中文描述: OP-AMP, 330 uV OFFSET-MAX, 88 MHz BAND WIDTH, PDSO8
封裝: 0.150 INCH, PLASTIC, SOP-8
文件頁數(shù): 9/12頁
文件大?。?/td> 304K
代理商: LT1468IS8
9
LT1468
APPLICATIO
S I
N
FOR
ATIO
U
The LT1468 may be inserted directly into many opera-
tional amplifier applications improving both DC and AC
performance, provided that the nulling circuitry is re-
moved. The suggested nulling circuit for the LT1468 is
shown below.
W
U
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with
the input capacitance to form a pole that can cause peaking
or even oscillations. For feedback resistors greater than
2k, a feedback capacitor of the value:
C
F
> (R
G
)(C
IN
/R
F
)
should be used to cancel the input pole and optimize dy-
namic performance. For applications where the DC noise
gain is one, and a large feedback resistor is used, C
F
should
be greater than or equal to C
IN
. An example would be a DAC
I-to-V converter as shown on the front page of this data
sheet where the DAC can have many tens of pF of output
capacitance. Another example would be a gain of
–1 with 5k resistors; a 5pF to 10pF capacitor should be
added across the feedback resistor. The frequency response
in a gain of –1 is shown in the Typical Performance curves
with 2k and 5.1k resistors with a 5pF feedback capacitor.
Layout and Passive Components
The LT1468 requires attention to detail in board layout in
order to maximize DC and AC performance. For best AC
results (for example fast settling time) use a ground plane,
short lead lengths, and RF-quality bypass capacitors
(0.01
μ
F to 0.1
μ
F) in parallel with low ESR bypass capaci-
tors (1
μ
F to 10
μ
F tantalum). For best DC performance, use
“star” grounding techniques, equalize input trace lengths
and minimize leakage (i.e., 1.5G
of leakage between an
input and a 15V supply will generate 10nA—equal to the
maximum I
B–
specification.)
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs. For inverting configurations tie the ring
to ground, in noninverting connections tie the ring to the
inverting input (note the input capacitance will increase
which may require a compensating capacitor as discussed
below.)
Microvolt level error voltages can also be generated in the
external circuitry. Thermocouple effects caused by tem-
perature gradients across dissimilar metals at the con-
tacts to the inputs can exceed the inherent drift of the
amplifier. Air currents over device leads should be mini-
mized, package leads should be short, and the two input
leads should be as close together as possible and main-
tained at the same temperature.
Make no connection to Pin 8. This pin is used for factory
trim of the inverting input current.
+
LT1468
1
5
100k
V
V
+
4
2.2
μ
F
0.1
μ
F
2.2
μ
F
0.1
μ
F
76
3
2
1468 AI01
Offset Nulling
+
LT1468
1468 AI02
R
G
R
F
C
IN
C
F
V
IN
V
OUT
Nulling Input Capacitance
Input Considerations
Each input of the LT1468 is protected with a 100
series
resistor and back-to-back diodes across the bases of the
input devices. If the inputs can be pulled apart, the input
current should be limited to less than 10mA with an
external series resistor. Each input also has two ESD
clamp diodes—one to each supply. If an input is driven
above the supply, limit the current with an external resistor
to less than 10mA.
The LT1468 employs bias current cancellation at the
inputs. The inverting input current is trimmed at zero
common mode voltage to minimize errors in inverting
applications such as I-to-V converters. The noninverting
input current is not trimmed and has a wider variation and
therefore a larger maximum value. As the input offset
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