參數(shù)資料
型號: LT1469CDF#TRPBF
廠商: Linear Technology
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC OPAMP 16BIT DUAL 90MHZ 12-DFN
標準包裝: 2,500
放大器類型: 通用
電路數(shù): 2
轉換速率: 22 V/µs
增益帶寬積: 90MHz
電流 - 輸入偏壓: 10nA
電壓 - 輸入偏移: 100µV
電流 - 電源: 4.1mA
電流 - 輸出 / 通道: 22mA
電壓 - 電源,單路/雙路(±): ±2.5 V ~ 18 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 12-WFDFN 裸露焊盤
供應商設備封裝: 12-DFN-EP(4x4)
包裝: 帶卷 (TR)
LT1469
13
1469fb
APPLICATIONS INFORMATION
Capacitive Loading
The LT1469 drives capacitive loads of up to 100pF in unity-
gain and 300pF in a gain of –1. When there is a need to
drivealargercapacitiveload,asmallseriesresistorshould
be inserted between the output and the load. In addition,
a capacitor should be added between the output and the
inverting input as shown in Figure 3.
Settling Time
The LT1469 is a single stage amplifier with an optimal
thermal layout that leads to outstanding settling per-
formance. Measuring settling even at the 12-bit level is
very challenging, and at the 16-bit level requires a great
deal of subtlety and expertise. Fortunately, there are two
excellent Linear Technology reference sources for settling
measurements—ApplicationNotes47and74.AppendixB
of AN47 is a vital primer on 12-bit settling measurements
and AN74 extends the state-of-the-art while concentrating
on settling time with a 16-bit current output DAC input.
The settling of the DAC I-to-V converter on the front page
was measured using the exact methods of AN74. The
optimum nulling of the DAC output capacitance requires
15pFacrossthe12kfeedbackresistor.Thetheoreticallimit
for 16-bit settling is 11.1 times this RC time constant or
2s. The actual settling time is 2.4s at the output of the
LT1469.
The RC output noise filter adds a slight settling time delay
butreducesthenoisebandwidthto1.6MHzwhichincreases
the output resolution for 16-bit accuracy.
Figure 3. Driving Capacitive Loads
+
VOUT
RF
RO ≥ (1 + RF/RG)/(2 CL 5MHz)
RF ≥ 10RO
CF = (2RO/RF)CL
CF
1/2 LT1469
VIN
1469 F03
CL
RG
RO
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