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參數(shù)資料
| 型號： | LT1714IGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 0K |
| 描述： | IC COMP R-RINOUT DUAL 16-SSOP |
| 標準包裝： | 2,500 |
| 系列： | UltraFast™ |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 2 |
| 輸出類型： | CMOS，補充型，滿擺幅，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2.4 V ~ 12 V，±2.4 V ~ 6 V |
| 電壓 - 輸入偏移（最小值）： | 4mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 2µA @ 5V |
| 電流 - 輸出（標準）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 7.5mA |
| CMRR, PSRR（標準）： | 70dB CMRR，80dB PSRR |
| 傳輸延遲（最大）： | 11ns |
| 磁滯： | 100mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
9
LT1713/LT1714
APPLICATIO S I FOR ATIO
WU
UU
Poor trace routes and high source impedances are also
common sources of problems. Keep trace lengths as
short as possible and avoid running any output trace
adjacent to an input trace to prevent unnecessary cou-
pling. If output traces are longer than a few inches,
provide proper termination impedances (typically 100
to 400
) to eliminate any reflections that may occur. Also
keep source impedances as low as possible, preferably
much less than 1k
.
The input and output traces should also be isolated from
one another. Power supply traces can be used to achieve
this isolation as shown in Figure 1, a typical topside layout
of the LT1713/LT1714 on a multilayer PC board. Shown is
the topside metal etch including traces, pin escape vias and
the land pads for a GN16 LT1713/LT1714 and its adjacent
X7R 0805 bypass capacitors. The V+, V– and GND traces
all shield the inputs from the outputs. Although the two V–
pins are connected internally, they should be shorted to-
gether externally as well in order for both to function as
shields. The same is true for the two V+ pins. The two GND
pins are not connected internally, but in most applications
they are both connected directly to the ground plane.
1714 F01
Figure 1. Typical LT1714 Topside Metal for Multilayer PCB Layout
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