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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | LT1715IMS |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 4/20闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC COMPARATOR 150MHZ DUAL 10MSOP |
| 妯欐簴鍖呰锛� | 50 |
| 绯诲垪锛� | UltraFast™ |
| 椤炲瀷锛� | 閫氱敤 |
| 鍏冧欢鏁�(sh霉)锛� | 2 |
| 杓稿嚭椤炲瀷锛� | CMOS锛屾豢鎿哄箙锛孴TL |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 2.7 V ~ 12 V |
| 闆诲 - 杓稿叆鍋忕Щ锛堟渶灏忓€硷級锛� | 2.5mV @ ±5V |
| 闆绘祦 - 杓稿叆鍋忓锛堟渶灏忓€硷級锛� | 6µA @ ±5V |
| 闆绘祦 - 杓稿嚭锛堟婧栵級锛� | 20mA |
| 闆绘祦 - 闈滄厠(t脿i)锛堟渶澶у€硷級锛� | 2mA |
| CMRR, PSRR锛堟婧栵級锛� | 70dB CMRR锛�80dB PSRR |
| 鍌宠几寤堕伈锛堟渶澶э級锛� | 9ns |
| 纾佹化锛� | 6mV |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 鍖呰锛� | 绠′欢 |
绗�1闋�绗�2闋�绗�3闋�鐣跺墠绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�
LT1715
12
1715fa
Figure 6. Additional External Hysteresis
鈥�
+
1/2 LT1715
INPUT
1715 F06
R2
VREF
R3
R1
APPLICATIONS INFORMATION
Unused Comparators
If a comparator is unused, its output should be left oa-
tingto minimize load current. The unused inputs can be
tied off to the rails and power consumption can be further
minimized if the inputs are connected to the power rails
to induce an output low. Connecting the inverting input
to VCC and the noninverting input to VEE will likely be the
easiest method.
Hysteresis
The LT1715 includes internal hysteresis, which makes it
easier to use than many other similar speed comparators.
The input-output transfer characteristic is illustrated in
Figure 5 showing the denitions of VOS and VHYST based
upon the two measurable trip points. The hysteresis band
makes the LT1715 well behaved, even with slowly moving
inputs.
The exact amount of hysteresis will vary from part to part
as indicated in the specications table. The hysteresis level
will also vary slightly with changes in supply voltage and
common mode voltage. A key advantage of the LT1715
is the signicant reduction in these effects, which is im-
portant whenever an LT1715 is used to detect a threshold
crossing in one direction only. In such a case, the relevant
trip point will be all that matters, and a stable offset volt-
age with an unpredictable level of hysteresis, as seen in
competing comparators, is useless. The LT1715 is many
times better than prior generation comparators in these
regards. In fact, the CMRR and PSRR tests are performed
by checking for changes in either trip point to the limits
indicated in the specications table. Because the offset
voltage is the average of the trip points, the CMRR and
PSRR of the offset voltage is therefore guaranteed to be
at least as good as those limits. This more stringent test
also puts a limit on the common mode and power supply
dependence of the hysteresis voltage.
Additional hysteresis may be added externally. The rail-
to-rail outputs of the LT1715 make this more predictable
than with TTL output comparators due to the LT1715鈥檚
small variability of VOH (output high voltage).
To add additional hysteresis, set up positive feedback
by adding additional external resistor R3 as shown in
Figure 6. Resistor R3 adds a portion of the output to the
threshold set by the resistor string. The LT1715 pulls the
outputs to +VS and ground to within 200mV of the rails
with light loads, and to within 400mV with heavy loads.
For the load of most circuits, a good model for the volt-
age on the right side of R3 is 300mV or +VS 鈥� 300mV,
for a total voltage swing of (+VS 鈥� 300mV) 鈥� (300mV) =
+VS 鈥� 600mV.
With this in mind, calculation of the resistor values needed
is a two-step process. First, calculate the value of R3 based
on the additional hysteresis desired, the output voltage
swing and the impedance of the primary bias string:
R3 = (R1||R2)(+VS 鈥� 0.6V)/(additional hysteresis)
Additional hysteresis is the desired overall hysteresis less
the internal 4mV hysteresis.
Figure 5. Hysteresis I/O Characteristics
VHYST
(= VTRIP
+ 鈥� VTRIP鈥�)
VHYST/2
VOL
1715 F05
VOH
VTRIP
鈥�
VTRIP
+
螖VIN = VIN
+ 鈥� VIN鈥�
VTRIP
+ + VTRIP鈥�
2
VOS =
V
OUT
0
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| LT1715IMS#PBF | 鍔熻兘鎻忚堪:IC COMPARATOR 150MHZ DUAL 10MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 绶氭€� - 姣旇純鍣� 绯诲垪:UltraFast™ 鐢�(ch菐n)鍝佸煿瑷撴ā濉�:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:2,500 绯诲垪:- 椤炲瀷:閫氱敤 鍏冧欢鏁�(sh霉):1 杓稿嚭椤炲瀷:CMOS锛屾帹鎸藉紡锛屾豢鎿哄箙锛孴TL 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.5 V ~ 5.5 V锛�±1.25 V ~ 2.75 V 闆诲 - 杓稿叆鍋忕Щ锛堟渶灏忓€硷級:5mV @ 5.5V 闆绘祦 - 杓稿叆鍋忓锛堟渶灏忓€硷級:1pA @ 5.5V 闆绘祦 - 杓稿嚭锛堟婧栵級:- 闆绘祦 - 闈滄厠(t脿i)锛堟渶澶у€硷級:24µA CMRR, PSRR锛堟婧栵級:80dB CMRR锛�80dB PSRR 鍌宠几寤堕伈锛堟渶澶э級:450ns 纾佹化:±3mV 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:6-WFBGA锛孋SPBGA 瀹夎椤炲瀷:琛ㄩ潰璨艰 鍖呰:绠′欢 鍏跺畠鍚嶇ū:Q3554586 |
| LT1715IMS#PBF | 鍒堕€犲晢:Linear Technology 鍔熻兘鎻忚堪:COMPARATOR DUAL 4NS MSOP-10 鍒堕€犲晢:Linear Technology 鍔熻兘鎻忚堪:COMPARATOR, DUAL, 4NS, MSOP-10 |
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| LT1715IMS#TRPBF | 鍔熻兘鎻忚堪:IC COMPARATOR 150MHZ DUAL 10MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 绶氭€� - 姣旇純鍣� 绯诲垪:UltraFast™ 鐢�(ch菐n)鍝佸煿瑷撴ā濉�:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:2,500 绯诲垪:- 椤炲瀷:閫氱敤 鍏冧欢鏁�(sh霉):1 杓稿嚭椤炲瀷:CMOS锛屾帹鎸藉紡锛屾豢鎿哄箙锛孴TL 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.5 V ~ 5.5 V锛�±1.25 V ~ 2.75 V 闆诲 - 杓稿叆鍋忕Щ锛堟渶灏忓€硷級:5mV @ 5.5V 闆绘祦 - 杓稿叆鍋忓锛堟渶灏忓€硷級:1pA @ 5.5V 闆绘祦 - 杓稿嚭锛堟婧栵級:- 闆绘祦 - 闈滄厠(t脿i)锛堟渶澶у€硷級:24µA CMRR, PSRR锛堟婧栵級:80dB CMRR锛�80dB PSRR 鍌宠几寤堕伈锛堟渶澶э級:450ns 纾佹化:±3mV 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:6-WFBGA锛孋SPBGA 瀹夎椤炲瀷:琛ㄩ潰璨艰 鍖呰:绠′欢 鍏跺畠鍚嶇ū:Q3554586 |
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