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| 型號： | LT1719CS8#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP R-R SINGLE 4.5NS 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | UltraFast™ |
| 類型： | 通用 |
| 元件數(shù)： | 1 |
| 輸出類型： | CMOS，滿擺幅，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 6 V |
| 電壓 - 輸入偏移（最小值）： | 2.5mV @ ±5V |
| 電流 - 輸入偏壓（最小值）： | 6µA @ ±5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 9mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 70dB CMRR，80dB PSRR |
| 傳輸延遲（最大）： | 4.2ns |
| 磁滯： | 7mV |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
LT1719
18
1719fa
–
+
–
+
C1
LT1719
A1
LT1636
VCC
2.7V TO 6V
2k
620Ω
220Ω
1MHz TO 10MHz
CRYSTAL (AT-CUT)
100k
200k
1720 F07
1.8k
2k
1k
0.1μF
OUTPUT
VCC
GROUND
CASE
Figure 8. Crystal Oscillator with a Forced 50% Duty Cycle
APPLICATIONS INFORMATION
±VTRIP Test Circuit
The input trip points test circuit uses a 1kHz triangle wave
to repeatedly trip the comparator being tested. The LT1719
output is used to trigger switched capacitor sampling of the
triangle wave, with a sampler for each direction. Because the
triangle wave is attenuated 1000:1 and fed to the LT1719’s
differential input, the sampled voltages are therefore 1000
times the input trip voltages. The hysteresis and offset are
computed from the trip points as shown.
Crystal Oscillator
A simple crystal oscillator using an LT1719 is shown on
the rst page of this data sheet. The 2k-620Ω resistor pair
set a bias point at the comparator’s noninverting input.
The 2k-1.8k-0.1μF path sets the inverting input node at
an appropriate DC average level based on the output.
The crystal’s path provides resonant positive feedback
and stable oscillation occurs. Although the LT1719 will
give the correct logic output when one input is outside
the common mode range, additional delays may occur
when it is so operated, opening the possibility of spurious
operating modes. Therefore, the DC bias voltages at the
inputs are set near the center of the LT1719’s common
mode range and the 220Ω resistor attenuates the feedback
to the noninverting input. The circuit will operate with any
AT-cut crystal from 1MHz to 10MHz over a 2.7V to 6V sup-
ply range. As the power is applied, the circuit remains off
until the LT1719 bias circuits activate, at a typical VCC of
2V to 2.2V (25°C), at which point the desired frequency
output is generated.
The output duty cycle of this circuit is roughly 50%, but
it is affected by resistor tolerances and to a lesser extent,
by comparator offsets and timings. If a 50% duty cycle is
required, the circuit of Figure 8 forces a 50% duty cycle.
Crystals are narrow-band elements, so the feedback to
the noninverting input is a ltered analog version of the
square wave output. Changing the noninverting reference
level can therefore vary the duty cycle. C1 operates as in
the previous example while A1 compares a band-limited
version of the output and biases C1’s negative input. C1’s
only degree of freedom to respond is variation of pulse
width; hence the output is forced to 50% duty cycle.
Again, the circuit operates from 2.7V to 6V. There is a
slight duty cycle dependence on comparator loading, so
minimal capacitive and resistive loading should be used
in critical applications.
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| LT1719IS6#TRM | 功能描述:IC COMP R-RINOUT SINGLE SOT23-6 RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 標(biāo)準(zhǔn)包裝:25 系列:- 類型:帶電壓基準(zhǔn) 元件數(shù):4 輸出類型:CMOS，開路漏極，TTL 電壓 - 電源，單路/雙路(±):2 V ~ 11 V，±1 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標(biāo)準(zhǔn)）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:12µs 磁滯:50mV 工作溫度:0°C ~ 70°C 封裝/外殼:16-DIP（0.300"，7.62mm） 安裝類型:通孔 包裝:管件 |
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