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參數(shù)資料
| 型號： | LT1721IGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | Dual/Quad, 4.5ns, Single Supply 3V/5V Comparators with Rail-to-Rail Outputs |
| 中文描述： | QUAD COMPARATOR, 4500 uV OFFSET-MAX, 7 ns RESPONSE TIME, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 317K |
| 代理商： | LT1721IGN |
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18
LT1720/LT1721
APPLICATIO
S I
N
FOR
ATIO
U
Optional Logarithmic Pulse Stretcher
The fourth comparator of the quad LT1721 can be put to
work as a logarithmic pulse stretcher. This simple circuit
can help tremendously if you don’t have a fast enough
oscilloscope (or control circuit) to easily capture 3ns pulse
widths (or faster). When an input pulse occurs, C2 is
charged up with a 180ns capture
2
time constant. The
hysteresis and 10mV offset across R3 are overcome
within the first nanosecond
3
, switching the comparator
output high. When the input pulse subsides, C2 dis-
charges with a 540ns time constant, keeping the compara-
tor on until the decay overrides the 10mV offset across R3
minus hysteresis. Because of this exponential decay, the
output pulse width will be proportional to the logarithm of
the input pulse width. It is important to bypass the circuit’s
V
CC
well to avoid coupling into the resistive divider. R4
keeps the quiescent input voltage in a range where forward
leakage of the diode due to the 0.4V V
OL
of the driving
comparator is not a problem.
Neglecting some effects
4
, the output pulse is related to the
input pulse as:
t
OUT
=
τ
2
l
n
{V
CH
[1 – exp (–t
P
/
τ
1
)]/(V
OFF
– V
H
/2)}
–
τ
1
l
n
[V
CH
/(V
CH
– V
OFF
– V
H
/2)]
+ t
P
where
t
P
= input pulse width
t
OUT
= output pulse width
τ
1
= R1 || R2 C2
the capture time constant
τ
2
= R2 C2
the decay time constant
V
OFF
= 10mV
the voltage drop across R1
V
H
= 3.5mV
LT1721 hysteresis
V
C
= V
IN
– V
FDIODE
the input pulse voltage after
the diode drop
V
CH
= V
C
R2/(R1 + R2)
the effective source voltage
for the charge
W
U
(1)
For simplicity, with t
P
<
τ
1
, and neglecting the very slight
delay in turn-on due to offset and hysteresis, the equation
can be approximated by:
t
OUT
=
τ
2
l
n
[(V
CH
t
P
/
τ
1
)/(V
OFF
– V
H
/2)]
For example, an 8ns input pulse gives a 1.67
μ
s output
pulse. Doubling the input pulse to 16ns lengthens the
output pulse by 0.37
μ
s. Doubling the input pulse again to
32ns adds another 0.37
μ
s to the output pulse, and so on.
The rate of 0.37
μ
s per octave falls out of the above
equation as:
t
OUT
/octave =
τ
2
l
n
(2)
There is
±
0.01
μ
s jitter
5
in the output pulse which gives an
uncertainty referred to the input pulse of less than 2%
(60ps resolution on a 3ns pulse with a 60MHz oscillo-
scope—not bad!). The beauty of this circuit is that it gives
resolution precisely where it’s hardest to get. The jitter is
due to a combination of the slow decay of the last few
millivolts on C2 and the 4nV/
√
Hz noise and 400MHz
bandwidth of the LT1721 input stage. Increasing the offset
across R3 or decreasing
τ
2
will decrease this jitter at the
expense of dynamic range.
The circuit topology itself is extremely fast, limited theo-
retically only by the speed of the diode, the capture time
constant
τ
1
and the pulse source impedance. Figure 14
shows results achieved with the implementation shown,
compared to a plot of equation (1). The low end is limited
by the delivery time of the upstream comparators. As the
input pulse width is increased, the log function is con-
strained by the asymptotic RC response but, rather than
becoming clamped, becomes time linear. Thus, for very
long input pulses the third term of equation (1) dominates
and the circuit becomes a 3
μ
s pulse stretcher.
(2)
(3)
2
So called because the very fast input pulse is “captured,” for later examination, as a charge on the
capacitor.
3
Assuming the input pulse slew rate at the diode is infinite. This effective delay constant, about 0.4%
of
τ
or 0.8ns, is the second term of equation 1, below. Driven by the 2.5ns slew-limited LT1721,
this effective delay will be 2ns.
4
V
is dependent on the LT1721 output voltage and nonlinear diode characteristics. Also, the
Thevenin equivalent charge voltage seen by C2 is boosted slightly by R2 being terminated above
ground.
5
Output jitter increases with inputs pulse widths below ~3ns.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LT1721IGN#PBF | 功能描述:IC COMP R-RINOUT QUAD 16-SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| LT1721IGN#TR | 功能描述:IC COMP QUAD R-R 4.5NS 16SSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| LT1721IGN#TRPBF | 功能描述:IC COMP R-RINOUT QUAD 16-SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| LT1721IS | 功能描述:IC COMP R-RINOUT QUAD 16-SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| LT1721IS#PBF | 功能描述:IC COMP R-RINOUT QUAD 16-SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
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